Incorporates M 101870 002
|Document Ref: MZB-3/4 (GE)
Date: May 1981
(Replaces Issue 2, August 1980)
Copyright in respect of this document is retained by Greenbank Electronics.
No unauthorised copies may be made.
(The design of the MZB-3 board itself is the property of Kemitron Electronics Ltd.)
92, New Chester Road, New Ferry, Wirral, Merseyside. L62 5AG Tel: 051-645 3391
2. ISBUS Compatibility
3. General Circuit Description
4. Detailed Circuit Description
4.1 Clock Oscillator
4.2 Reset Circuit
4.3 CPU and Power on Jump Decoder
4.4 Boot PROM and Controller
4.6 Power Supplies
6. Fault Finding
8. Appendix 1: Use of 4 MHz Z80A
8.1 Factors Influencing Choice of Frequency Drg. No. 101871: Buffer Delays 8.2 Access Time Drg. No. 101872: Access Timing 8.3 Dynamic RAMs Drg. No. 101873: Refresh Timing 8.4 Modification to Permit 2/4 MHz Operation Drg. No. 101874: Downgrade From 2-4 MHz
9. Appendix 2: Use of 6 MHz CPU Clock
10. Circuit Diagrams, Drawings Etc.
101810 Sheet 1: Clock Oscillator
2: Reset Circuitry
3: CPU and Power on Jump
4: Boot PROM and Controller
6: Power Supplies
101830: Assembly Drawing (Component Layout) 101840: Parts List
ADDITIONAL NOTE TO THE FOURTH EDITION OF THE MZB-3 MANUAL 1982
Throughout this manual mention is made of the caution which must be employed when operating the MZB-3 card at 4.0 MHz.
However the recommendation now for Interak 1, and indeed the majority of all other uses, is to operate the card at 4.0 MHz, and to dispense entirely with any modifications to lower the frequency.
Operational experience has confirmed the designer's original contention that 100% satisfactory results can be obtained at this frequency. This is readily explained when it is realised that modern memory devices are vastly superior to the types which were generally available some years ago.
Therefore it is suggested that the inconvenience and reduced performance which is suffered when the card is modified for half-speed operation need no longer be tolerated, and thus the card should simply be assembled in the standard way for 4.0 MHz operation.
D.M.P. July 1982.
2003-10-10 Converted to HMTL.
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