8.1 Factors Influencing Choice of Crystal (Clock) Frequency.
8.1.1
Throughout this document the CPU chosen has been the higher speed version 4.0 MHz, as opposed to the 2.5 MHz version. This decision was based on economic grounds: At the time of writing a quartz crystal of 2.0 or 2.5 MHz is about £1.00 dearer than the 4.0 MHz type, and the 2.5 MHz CPU is only about £1.00 cheaper than the 4.0 MHz version.8.1.2
In other words, provided the quartz crystal price is considered as well, there is little or no difference in total cost whatever speed CPU is chosen, and so the choice of the higher performance CPU represents the best value for money.8.1.3
As will be discussed in the various sections which follow, increased speed can often be more trouble than it is worth, and accordingly a method of modifying the MZB-3 circuit is described. The modification requires no extra parts, yet provides the option of 2.0 MHz or 4.0 MHz operation. It is fairly easy to make a fast circuit run slowly ('downgrade' to 2.0 MHz), but difficult or impossible to do the reverse, and this is another vindication of the decision to specify the 4.0 MHz CPU as standard.8.2 Access Time.
8.2.1
The main difficulty with 4.0 MHz operation is 'Access Time' restrictions. (The Access Time is the time it takes for a memory device to produce its correct data once its address lines are correct). Diagram No. 101871 'MZB-3 Buffer Delays in a Typical System' (Page 24), shows how buffer delays mount up. In the system taken as the example, up to 80 ns can be lost. Assuming that it is a 2516 which is being addressed, and further assuming that it can only guarantee valid data 450 ns later, then the CPU must be prepared to wait 450 + 80 = 530 ns before it can expect valid data on its data lines.8.2.2
The problem is aggravated when dynamic memories are being used. The address circuits generally used only present the address to the RAM after NMREQ has gone low, which is later than the time the addresses are first valid, the case considered in Section 8.2.1 above.8.2.3
As the CPU speed increases, so the rate at which it expects data increases, and shorter and shorter memory access times result.8.2.4
In order to ensure that the 'worst case' specifications are met, as far as is practical, it is necessary to study all of the various device data sheets extensively. Simply building a system and testing it to show it works is not good enough, and can give rise to vague complaints such as 'when I use this instruction the program sometimes fails', or 'After a few hours' use, the memory begins to fade, but only in warm weather' etc. Problems with dynamic RAMs used to be so common that they were given the name 'Memory Plague' by some suppliers.8.2.5
Some very well-known names are responsible for 'suspect' designs of this nature - you can be sure something is wrong if it is necessary to swap memory ICs around on the board to make it work, or to use only a particular make of buffer, with a given batch code etc.8.2.6
It will be shown during the course of these notes that correct operation cannot be guaranteed with a 4.0 MHz CPU clock frequency, for 450 ns static RAMs and EPROMs. Even the fastest dynamic RAM generally available (type 4116-2, 150 ns) cannot be used at this frequency, as it requires a NRAS precharge time of at least 100 ns, and the CPU can only provide 95 ns when it is running at 4.0 MHz. However, actual operating experience entirely contradicts this:8.2.7
It has been found in practice that this board, and its companion dynamic RAM card MXD-2, operate satisfactorily at 4.0 MHz, but it should be stressed that this is due to the good nature of the chip manufacturers, who almost invariably supply chips which are vastly superior to their 'worst case' data sheet limits.8.2.8
The MZB-3 Memory Access Timing Diagram is to be found on page 26 . The full details are given in the appropriate manufacturers data sheets, and only the salient features are reproduced here. The timing illustrated is the most stringent of all the Z80/MK3880 cycles: the '!M1' or 'Op-Code Fetch' cycle, which is shorter than the subsequent memory.8.2.9
The table to the right of the diagram lists the relevant parameters at the three clock frequencies, and concludes that the access time for the memories required to work with the CPU at 2.0 MHz, 2.5 MHz, and 4.0 MHz are 725 ns, 525 ns, and 275 ns, respectively. Thus at 2.0 and 2.5 MHz, the standard 450 ns 2114s, 2516s etc. are suitable, but at 4.0 MHz the requirement shrinks to 275 ns, and prohibits the use of the common memory devices.8.2.10
The on-board 'boot PROM' is mounted on the MZB-3 board before the buffers, and is therefore not subject to the buffer delays. This means that the figure of 80 ns for T used on Drawing No. 101872 B can be reduced to zero. Thus the maximum access times for IC11 with the CPU clock at 2.0, 2.5, and 4.0 MHz, are 805 ns, 605 ns, and 355 ns respectively. The main conclusion, which must be drawn, is that even for the on-board PROM 4.0 MHz is too fast if a standard 450 ns type is used.8.2.11
Thus at 4.0 MHz it is likely (depending on actual system delays), that a 350 ns component is needed for IC11, and 250 ns for off-board memories.8.2.12
To permit the use of standard 450 ns memories, one possibility is to add 'WAIT' states to the circuit. At 4.0 MHz each WAIT-state added extends the access time by 250 ns, so a single WAIT state (for all accesses, not just !M1) will be sufficient.8.2.13
As the WAIT states slow the CPU down they tend to act so as to reduce some of the benefit of operating at 4.0 MHz. (There is usually a net benefit however, as when the CPU has finished waiting it can then resume operation at top speed; a slower CPU is slower all the time).8.2.14
The ideal arrangement for entering WAIT states is for the (slow) memory to pull the A34 (NWAIT) bus line low for as long as it needs, timing either by a monostable, or some method of counting clock pulses.8.2.15
As none of the 'Kemitron' boards provide this facility, on the grounds of avoiding undue complication, no further details are given here. Extra information regarding WAIT states is given in the appropriate data sheets and books.8.2.16
IC11 on the MZB-3 board is also affected, so if this IC is fitted then extra WAIT states must be provided for this component also.8.3 Dynamic RAMs.
8.3.1
Dynamic RAMs offer the great benefits of very low cost, and reduced power consumption. They are however a little more difficult to understand, and the task of circuit design is more complicated.8.3.2
The user should be careful not to make the mistake of thinking that for example a 250 ns dynamic RAM will give any benefit over a 450 ns static RAM, when considering access timing. There are various parameters, such as address multiplexer delays, precharge times, and cycle times, for dynamic RAMs, which must also be taken into account.8.3.4
With a 4.0 MHz CPU the access time depends on the various buffer, decoding, etc. delays, and it is likely that the 4116-2 (150 ns) type will be needed, which is disproportionately expensive, due to the high popularity of the 'normal' 4116-4 (250 ns) type, which keeps its price down.8.3.5
The main problem with the use of dynamic RAMs is not directly related to the question of access times, but occurs during the 'refresh cycle'. See Drawing No, 101873 'MZB-3 Refresh Cycle' Timing', on page 28.8.3.6.1
The diagram illustrates the main essentials of the CPU refresh cycle. As NMREQ is used directly to generate the row address strobe NRAS, the time for which this is low ('TR' on the diagram) is of importance.8.3.6.2
For CPU clock frequencies of 2.0, 2.5, and 4.0 MHz, this parameter (TR) is 460 ns, 360 ns, and 220 ns, respectively. The NRAS required is required by the 4116-4, and is 250 ns for this device, and so it is unsuitable. (The 4116-4 will already have been eliminated for 4.0 MHz operation on the grounds of inadequate access time, so it will not matter that it must be eliminated again here.)8.3.7
The Precharge times ('TP') for the three frequencies are 210 ns, 160 ns and 95 ns. It will be seen that the worst device (4116-4) can easily be used at 2.0 MHz, and possibly 2.5 MHz, since 150 ns for the 4116-4 is less than the 210 ns and 160 ns limits, but the 95 ns available at 4.0 MHz is inadequate for any of the 4116s, even the fastest.8.3.8
To summarise, the clock frequency of 2.0 MHz is ideal for static 450 ns memories (e.g. 2708,2516,2114) and for the cheapest 4116-4 250 ns dynamic RAMs, but a CPU clock frequency of 4.0 MHz requires WAIT states to be added, for all but the very fastest of the static memories, and prohibits entirely the use of all the dynamic memories listed. (But remember some people neither know nor care about these detailed design points, and enjoy perfectly satisfactory operation with a 4.0 MHz CPU clock.)8.3.9
Adding WAIT states cannot help the dynamic RAM precharge problem, since WAIT states cannot be inserted in the CPU refresh cycle.
(Note, this is a defect in the Z80 CPU chip itself, not a defect in the MZB-3 boards)8.3.10
There are methods of extending the precharge time and so permitting the use of dynamic RAMs with a 4.0 MHz clock, but the usual solutions involve the use of high speed 'Schottky' flip-flops, and the '!Ml' signal, which is not an allocation on the ISBUS standard.8.3.11
Therefore, based on the assumption that the user is reading these notes simply to get his MZB-3 board going, the following two solutions to the problems raised are offered:(i) Ignore the precharge problem, and take a chance with the fastest 4116 you can obtain. The 4116-2 needs 100 ns precharge and the CPU at 4.0 MHz offers 95 ns so in fact there is every chance that a typical 4116-2 will not notice the missing 5 ns, which after all is an exceedingly small time. (Even something travelling at the speed of light couldn't cover a couple of metres in 5 ns!)
(ii) Make a modification, as described in Section 6.4 below so that clock frequencies of both 2.0 MHz and 4.0 MHz are readily available. In this way 2.0 MHz can be used while the system is being tested, and 4.0 MHz can be used for experimentation.
8.4 Modification to permit 2.0 MHz / 4.0 MHz operation.
8.4.1
IC15b (half D flip-flop) serves no useful purpose in the circuit as it stands, and it may be released to act as a divide-by-two counter to divide the 4.0 MHz clock down to a 2.0 MHz signal. Either of these frequencies can then be selected as the CPU clock.8.4.2
The modified circuit is shown on drawing 101874 'MZB-3 Downgrade from 4.0 MHz to 2.0 MHz', on page 31, and the following step-by-step instructions should be read in conjunction with the information on the drawing.8.4.3
Isolate pin ‘IQ of IC15b by cutting tracks.8.4.4
Reconnect IC15a to IC16 pin 4, and thus restore the circuit to virtually its original state.8.4.5
Isolate IC9 pin 4.8.4.6
Connect IC9 pin 4 to IC15b pin 11.8.4.7
Connect IC15b pin 8 to IC15b pin 12.8.4.8
Connect IC15b pin 10 and IC15b pin 13 to +5V (e.g. IC15b pin 14). It is not necessary to use a resistor in series to make the +5V connection for the reasons given at the foot of page 16.8.4.9
Connect IC9 pins 9,11 to IC9 pin 4 via jumper wire JM1 for 4.0 MHz operation as before.8.4.10
Alternatively connect IC9 pins 9,11 to IC15b pin 9, via jumper wire JM2 for operation at 2.0 MHz.8.4.11
The changeover from 4.0 MHz to 2.0 MHz may be by means of a switch if desired, but note this switch must not be operated whilst the CPU is running as data may be corrupted during the changeover. If, during the changeover the CPU is stopped so effectively that M1 cycles cease, then it will prove impossible to restart the CPU without switching the system off. (This is because the Reset Circuit (Drg. No. 101810 sheet 2 page 34) needs the !ZM1 input on pin 9 of IC14c to let it produce the clock, pin 3 of IC15a: no clock = no reset'.) At switch-on the R8-C5 combination provides another reset, regardless of the presence or absence of !ZM1.