SUBTTL INTERNAL DISK CONTROLLER DEFINITIONS ;**************************************************************************** ; ; INTERNAL BOARD LEVEL PARAMETERS INCLUDE MODULE FOR THE JADE ; DOUBLE D DISK CONTROLLER BOARD. INCLUDE THIS MODULE TO DEFINE ANY ; PARAMETERS WITH SOFTWARE TO EXECUTE ON THE BOARD'S Z-80 PROCESSOR. ; ;**************************************************************************** ; ; REVISIONS: ; ; 1.0 - 19 JUL 82 ; RELEASE ; ; 1.1 - 14 FEB 83 ; MODIFIED FOR REV C BOARD: ; CHANGED DEFINITIONS TO ALLOW FOR 1795/7 CHIP ; ; 1.2 - 23 OCT 83 GRH ; CLEANED UP, ADDED HEADER GRAPHICS ; ; 1.3 - 30 OCT 85 GRH ; Rearranged definitions. Added double sided hooks. ; ;**************************************************************************** ;============================================================================ ; ; DISK DRIVE PARAMETERS ; ;============================================================================ TMSTP: EQU 8 ;STEPPER INTERVAL (ms) (BIM) TMSTPC EQU 80 ; " " (100US) (DCM) TMDBR: EQU 1 ;DELAY BEFORE READ (ms) (BIM) NBTRK: EQU 80 ;MAXIMUM # STEPS TMHLD EQU 350 ;HEAD ENGAGE TIME (100US) (DCM) TMALS EQU 80 ;DELAY AFTER LAST STEP (100US) (DCM) TMMTO EQU 1 ;MOTOR START UP DELAY (100US) (DCM) TMPLD EQU 1200 ;PHASE LOCK RECOVERY (100US) (DCM) TMSAW EQU 10 ;STEP AFTER WRITING (100US) (DCM) ; ; TIMING CONSTANTS: ; TMRFC EQU 19H ;1ST PASS TMRNC EQU 1CH ;NORMAL PASS ; ; RETRY VALUES: ; RTYSK EQU 5 ;REPOSITION HEAD ON RETRY RTYLS EQU 9 ;LAST REPEATED RETRY ;============================================================================ ; ; INTERNAL MEMORY ASSIGNMENTS ; ;============================================================================ BANKL: EQU 1024 ;1K BANK LENGTH BANK0: EQU 0 ;LOWER BANK BASE ADDR BANK1: EQU BANK0 + BANKL ;UPPER BANK BASE ADDR ; FMTBG EQU BANK1 + 300H ;FORMAT BUFFER FMTPS EQU FMTBG + 8 ;FORMAT START ADDR ; ; BOOTSTRAP COMMUNICATION ; BEHOM: EQU 1 ;HOME ERROR BERDA: EQU 2 ;READ ERROR A BERDB: EQU 4 ;READ ERROR B ; ; DISK CONTROLLER MODULE (DCM) LINKAGE ; DCMSS: EQU 4 ;1ST DCM SECTOR DCMBG: EQU BANK1+3 ;DCM COLD START ENTRY DCMLN: EQU 1024 ;DCM LENGTH ;============================================================================ ; ; PORTS ; ;============================================================================ BLSTS: EQU 0 ;BOARD LEVEL STATUS PORT ; ; D7 D0 ; |DCN|2SD|MOF|EIA|INT|TST|US1|US0| ; ^ ^ ^ ^ ^ ^ ^ ^_____ 179X DATA INVERT (1) ; | | | | | | |_________ USER SWITCH 1 (SPARE) ; | | | | | |_____________ TEST MODE (1) ; | | | | |_________________ HOST INTERRUPT REQUEST (1) ; | | | |_____________________ EIA PORT INPUT ; | | |_________________________ MOTOR OFF (1) ; | |_____________________________ 2 SIDED DRIVE FLAG (1) ; |_________________________________ DISK CHANGE FLAG (1) ; ; THE FOLLOWING DEFINES EACH BIT & FUNCTION OF THE BOARD ; STATUS PORT (BLSTS) BSUS0 EQU 00000001B ;USER SWITCH 0 - 179X INVERT BSUS1 EQU 00000010B ;USER SWITCH 1 - SPARE BSTST EQU 00000100B ;TEST MODE BSINT EQU 00001000B ;HOST INT REQ BSEIA EQU 00010000B ;EIA SIGNAL INPUT BSMOF EQU 00100000B ;MOTOR OFF INDICATOR BSTSD EQU 01000000B ;2 SIDED DRIVE FLAG BSDCN EQU 10000000B ;DISK CHANGE ;============================================================================ BLCTL: EQU 0 ;BOARD LEVEL CONTROL PORT ; ; |PCB|PCA|DAS|DDE|EIA|DSE|DSB|DSA| ; \_____/ ^ ^ ^ ^ \_____/ ; | | | | | |______ DRIVE SELECT ADDRESS (0..3) ; | | | | |____________ DRIVE SELECT ENABLE ; | | | |________________ EIA OUTPUT PORT ; | | |____________________ DOUBLE DENSITY ENABLE ; | |________________________ DIRECTION & SIDE SELECT ; | 1: IN/SIDE 1, 0: OUT/SIDE 0 ; |______________________________ PRECOMP SELECT (0..3) ; ; THE FOLLOWING ASSIGNS EACH BIT POSITION & FUNCTION OF THE ; BOARD CONTROL PORT (BLCTL). ; BCDSA EQU 00000001B ;DRIVE SELECT A (2^0) BCDSB EQU 00000010B ;DRIVE SELECT B (2^1) BCDSE EQU 00000100B ;DRIVE SELECT ENABLE BCEIA EQU 00001000B ;EIA SIGNAL OUT BCDDE EQU 00010000B ;DOUBLE DENSITY ENABLE BCDAS EQU 00100000B ;DIRECTION & SIDE BCPCA EQU 01000000B ;PRECOMP SELECT A BCPCB EQU 10000000B ;PRECOMP SELECT B BCDR0: EQU 0 ;DRIVE 0 SELECT ; ; FUNCTION ASSIGNMENTS: ; BCDSN EQU BCDSA + BCDSB ;DRIVE MASK BCSDS EQU 0 ;SINGLE DENSITY BCDDS EQU BCDDE ;DOUBLE DENSITY BCPCH EQU BCPCA ;PRECOMP HEAVY BCPCM EQU BCPCB ;PRECOMP MEDIUM BCPCL EQU BCPCA + BCPCB ;PRECOMP LIGHT BCPCZ EQU 0 ;PRECOMP OFF ;============================================================================ WDCMD: EQU 4 ;179X COMMAND REGISTER ; DCHDL: EQU 00011000B ;LOAD HEAD DCHDU EQU 00010000B ;HEAD UNLOAD ; ; THE READ & WRITE SECTOR CMDS NOW HAVE SIDE 1 SELECT BIT SET FOR ; 1791..4 CHIPS, HOWEVER THE SIDE CHECK ENABLE BIT IS FALSE, SO IT ; BECOMES A DON'T CARE. THIS IS NEEDED FOR COMPATABILITY WITH THE 1795..7 ; CHIP, WHICH USES THE SIDE SELECT BIT FOR DETERMINING SECTOR SIZE & MUST ; BE A 1 FOR 128 BYTES PER SECTOR. (0= 256 BYTES) ; DCRDS EQU 10001000B ;READ SECTOR DCRMSº EQÕ 10011000Â ;REAÄ MULIPLÅ RECORDS DCWRS EQU 10101000B ;WRITE SECTOR ; DCRDA EQU 11000000B ;READ TRACK ADDR DCSTS: EQU 11010000B ;TERMINATE OPERATION & READ TYPE 1 STATUS DCIFI EQU 11011000B ;FORCED INTERRUPT - NOT USED DCWRT EQU 11110000B ;WRITE TRACK FORMAT ;============================================================================ WDSTS: EQU 4 ;179X STATUS REGISTER ; ; STATUS BIT DEFINITIONS ; TYPE I: ; CSDNR EQU 10000000B ;DRIVE NOT READY CSWRP EQU 01000000B ;WRITE PROTECTED CSHLD EQU 00100000B ;HEAD LOADED CSSKE EQU 00010000B ;SEEK ERROR CSCRC EQU 00001000B ;CRC ERROR CSTK0 EQU 00000100B ;TRACK 0 CSINDX EQU 00000010B ;INDEX CSBSY EQU 00000001B ;BUSY ; ; TYPE II & III ; CSTYPE EQU 00100000B ;RECORD TYPE CSWFLT EQU 00100000B ;WRITE FAULT CSRNF EQU 00010000B ;RECORD NOT FOUND CSLDE EQU 00000100B ;LOST DATA ERR CSDRQ EQU 00000010B ;DATA REQUEST ; ; DISK STATUS MASKS ; DMRER: EQU 10011101B ;READ ERROR TEST MASK DMWER EQU 11111101B ;WRITE ERROR TEST DMFER EQU 11100100B ;FORMAT ERROR TEST DMTK0: EQU 00000100B ;TRACK 0 TEST DMHDL EQU 00100000B ;HEAD LOAD TEST DMDNR EQU 10000000B ;DRIVE NOT READY DMLDE EQU 00000100B ;LOST DATA ERR ;============================================================================ WDTRK: EQU 5 ;179X TRACK REGISTER ;============================================================================ WDSEC: EQU 6 ;179X SECTOR REGISTER ;============================================================================ WDDTA: EQU 7 ;179X DATA REGISTER ;============================================================================ XPSTP: EQU 8H ;STEP PULSE GENERATOR ; (DATA = DON'T CARE) ;============================================================================ XPMTO: EQU 10H ;MOTOR OFF GENERATOR ; (DATA = DON'T CARE) ;============================================================================ XPIRR EQU 20H ;RESET HOST INTERRUPT REQUEST FF ; (DATA = DON'T CARE) ;============================================================================ XPMTX: EQU 40H ;MOTOR ON GENERATOR ; (DATA = DON'T CARE) ;============================================================================ XPDSH: EQU 80H ;DATA SYNC HOLD ; (DATA = DON'T CARE)