.TITLE	TIMOUT
/
/  23 FEB 77 - PAUL HENDERSON
/
/  ROUTINE TO TRY TO DETERMINE THE SYSTEM DELAY IN PROCESSING
/  I/O REQUESTS TO THE FAST CLOCK HANDLER
/
APISLT=77-40
FCRS=702601		/ FAST CLOCK: RESET BUFFER TO ZERO, CLEAR FLAG,
			/		STOP CLOCK
FCLG=702607		/ FAST CLOCK: CLEAR FLAG, LOAD CLOCK BUFFER FROM AC,
			/		START CLOCK
FCST=702621		/ FAST CLOCK: STOP
FCRB=702632		/ FAST CLOCK: READ CLOCK BUFFER INTO AC
FCCF=702624		/ FAST CLOCK: CLEAR FLAG
FCSF=702641		/ FAST CLOCK: SKIP ON FLAG
FCEI=702642		/ FAST CLOCK: ENABLE INTERRUPTS
FCDI=702644		/ FAST CLOCK: DISABLE INTERRUPTS
/
SET=ISZ			/ SET FLAG NON-ZERO (NEVER SKIPS)
/
TIMOUT	SNAP	1,400
	CLA
	FCDI			/ MAKE SURE WE'RE TURNED OFF
	FCLG
	CAL	FCPUT		/ MAKE THE TIME REQUEST
	FCRB
	DAC	ONE
	FCRB
	DAC	TWO		/ DO IT TWICE, IN CASE OF SKEW
	CAL	WTFOR
	FCRB
	DAC	THREE
	FCRB
	DAC	FOUR
	FCST
	FCRB
	DAC	FIVE
	SNAP	2,0,EV,FIVE
	CAL	(10
/
FCPUT	3100;	EV; 35; 0; 1; 0
WTFOR	20;	EV
EV;ONE;TWO;THREE;FOUR;FIVE
	.END	TIMOUT