midas assembler_. extended memory, part 4. /constant designators svs, dap svx jsp sav /save word info gsj gsi wrd fct psn fcn def rlc fcr fci tt ct qt bt rt syl jmp svx svx, jmp . lp, jsp svs lp1, jsp sts rp1 rp1 init rt, rp jmp rsw /evaluate constant syllable rp1, law 1 /tab or c. r. rp, add (rr /r. p. dap cox jsp evl flex usc jsp rss+1 idx chc lac pss sza i jmp co8 spi /def in IO jsp udf c12, lac nco dac t2 jmp co4 co2, extend lac i t2 sad wrd jmp co6 co4, idx t2 sas (con+1 jmp co2 /define new constant co1, lac wrd extend dac i nco lac nco dac t2 sub one dac nco extend lac i dpx and (177777 sub nco sma jsp sce jsp crk lio (600000 co7, rir 2s isp t1 jmp co7 dio t1 /mask jsp rcj xor rct extend xor i cr5 and t1 extend xor i cr5 extend dac i cr5 c10, idx nca co5, lac pss sza i jmp c22 lac (con extend add i cn5 sub t2 cli rcl 1s rar 1s dio nmr and (7777 dac num jsp rlck flex irc spi i jsp ilr c22, jsp uns jmp svx lac pss sza cox, jmp . law i 1 dac def jmp cox co8, spi /def on pass 1 jmp c10 jmp c12 co6, jsp crv /check rel. agreement sad rlc jmp co5 jmp co4 crv, dap cx jsp crk extend lio i cr5 cr4, ril 2s /calculate relocation isp t1 jmp cr4 jsp erk cx, jmp . crk, dap crx /subr to reference crl lac (con sub t2 scr 3s add (crl dac cr5 cla scl 3s cma sub one dac t1 crx, jmp . cr5, 0 cn5, 0 cn6, 0 cn8, 0 va4, 0 va7, 0 /pseudo-instruction constants cns| ondrum lac indef spa jmp ilf lac cn5 sad (cor+ncn+ncn+ncn jmp tmc dac cn6 idx cn6 dac cn8 idx cn8 lac (con+1 dac t2 lac rli add ofstr rar 1s add loc add ofst lio pss rir 1s spi i jmp cn1 extend sad i cn5 jmp cn7 cld, error alm, alh, flex cld cn1, extend dac i cn5 lac nca add loc add ofst extend dac i cn6 jmp cnd cn2, extend lio i t2 dio wrd jsp crv dac rlc jsp tb3 cn7, law i 1 add t2 dac t2 sas nco jmp cn2 lac loc add ofst extend dac i cn8 cnd, extend lac i cn5 and (-600000 cma extend add i cn6 add aml dac aml dzm nca lac (con dac nco law 3 add cn5 dac cn5 extend lac i cn6 jmp cnb endrum /pseudo-instruction variables var| ondrum lac indef spa jsp ilf idx va4 dac va7 idx va4 sad (vor+nvo+nvo jmp tmv lac pss sza i jmp va2 lac loc extend sad i va7 jmp va6 vld, error alm, rst, flexo vld va2, lac loc /pass 1 extend dac i va7 load evp, st-1 jmp vai va3, extend lac i sp2 and (600000 sas (200000 jmp vai extend lac i sp1 and (600000 sza jmp va3a extend lac i evp add loc add ofst extend dap i evp lac rli add ofstr rar 1s extend add i sp2 va3b, sub (200000 extend dac i sp2 vai, idx evp dac sp1 dac sp2 idx sp2 dac evp idx evp sas (low+2 jmp va3 lac loc add vct extend dac i va4 va6, dzm vct /pass 2 extend lac i va4 extend sub i va7 add aml dac aml extend lac i va4 endrum jmp cnb cnb, lio rli dio rlc dac wrd jmp b5 va3a, sas (600000 jmp vai lac rli add ofstr rar 1s extend add i evp add loc add ofst and (407777 extend dac i evp extend lac i sp2 jmp va3b dim| lac pss /pseudo-instruction dimension sza jmp itt jsp sts rsw rst init lt, di1 init rt, di2 jmp rsw di1, lac syl lio let spa+spi i 5-skp jsp ilf szf 2 dac gsj jsp sav sym l sym r gsj jmp rsw di2, jsp evl flex usd spi jsp udf lac gsi sza jsp ilf lac vct dac tvl add wrd dac vct jsp uns jmp rsw jsp es jmp di4 spi>>05<>05<>05<>05<>05<>05<