Concise Atari ST 68000 Programmer's Reference Guide
The Motorola MC68000 series of microprocessors rationalize instruction code allocation by segmenting the 16-bit Operation Word into five smaller blocks, each of which has a fairly consistent meaning.
Operation word instruction
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Type dreg dmod smod sreg
Instruction Word Parsing Analysis Type
The types 0 to 15 instruction codes (16 classes) are allocated as follows:
15 14 13 12 Type Instructions Range 0 Bit manipulation, Move Peripheral and Immediate instructions 1 Move byte Instructions 2 Move longword instructions 3 Move word instructions 4 Miscellaneous instructions 5 Add Quick, Subtract Quick, Set conditionally and Decrement instructions 6 Branch conditionally instructions 7 Move Quick instructions 8 Or, Divide and Subtract decimal instrs. 9 Subtract, Subtract extended instrs. 10 Unassigned 11 Compare, Exclusive Or instructions 12 And, Multiply, Add decimal and Exchange instructions 13 Add, Add extended instructions 14 Shift and Rotate instructions 15 Unassigned
Dreg
11 10 9 dreg
Dreg has three main uses, normally holding the destination address in the general move instruction, one of the two register numbers for use in the specified instruction or embedded data for use in the add and subtract quick instructions.
Dreg only refers to a register in those instances where the instruction has two register operands.
Dmod
8 7 6 dreg
Dmod has two main uses, specifying the effective address mode of the destination operand in the general move instruction or, in most other cases it defines the size of the operation to be performed.
Smod
5 4 3 smod
Smod usually defines the effective address mode of the instruction, the source operand for the move instruction.
Sreg
2 1 0 sreg
Sreg defines the effective address register, usually the source.
