This section lists the hardware registers and Operating System
(OS) shadow registers.
In the following descriptions, true always refers to a bit whose
value is 1.
There are two versions of the GTIA: The NTSC (United States TV standard) and PAL (one of the European TV standards). The PAL GTIA has been designed so that most programs will run without modification. However, some differences may be noticeable. There is a hardware register (PAL) which a program can read to determine whether it is PAL or NTSC and adjust accordingly.
PAL (D014)
D7 D6 D5 D4 D3 D2 D1 D0 X X X X X Not used 1 1 1 NTSC (US TV) 0 0 0 PAL (European TV)
This byte can be read by a program to determine which type of system the program is running on.
<The SECAM data sheet says that all 'not used' bits are read as zero on D7-4 and as one on D3-0. Thus the register above reads hex 0F for NTSC and 01 for PAL and SECAM.>
NMIEN (Non Maskable Interrupt Enable)(D40E)
This address writes data to the NMI Interrupt enable bits.
0 = disabled (masked)
1 = enabled
| D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 | |
| Not used | ||||||||
| Vertical Blank Interrupt Enable. This bit is cleared by Power Reset, and may be set or cleared by the processor. | ||||||||
| Display List Instruction Interrupt Enable. This bit is cleared by Power Reset, and may be set or cleared by the processor. | ||||||||
SYSTEM RESET Button Interrupt
This interrupt is always enabled. The SYSTEM RESET button should
not be pressed during power turn on.
(Set to hex 40 by OS IRQ code.)
NMIST (Non Maskable Interrupt Status)(D40F)
This address reads the NMI Status Register (Read by OS NMI code).
0 = no interrupt
1 = interrupt
D7 D6 D5 D4 D3 D2 D1 D0 Not used This bit identifies an NMI Interrupt caused by: the SYSTEM RESET button. the beginning of vertical blank. bit 7 of a Display List Instruction.
NMIRES (NMI Status Register Reset)(D40F)
This write address resets the Non Maskable Interrupt Status Register (NMIST).
D7 D6 D5 D4 D3 D2 D1 D0 Don't care (written by OS NMI code)
IRQST (IRQ Interrupt Status)(D20E)
This address reads the data from the IRQ Interrupt Status
Register.
0 = no interrupt
1 = interrupt
D7 D6 D5 D4 D3 D2 D1 D0 Timer 1 Interrupt Timer 2 Interrupt Timer 4 Interrupt Serial Output (Byte) Transmission Finished Interrupt * Serial Output Data Needed Interrupt Serial Input Data Ready Interrupt Other Key Interrupt Break Key Interrupt
NOTE: Used for generation of 2 stop bits. See IRQ description in section II (no direct reset on bit 3).
IRQEN (IRQ Interrupt Enable)(D20E)
This address writes data to the IRQ Interrupt Enable bits.
0 = disable, corresponding IRQST bit is set to 1
1 = enable
D7 D6 D5 D4 D3 D2 D1 D0 Timer 1 Interrupt Enable Timer 2 Interrupt Enable Timer 4 Interrupt Enable Serial Out Transmission Finished Interrupt Enable Serial Output Data Needed Interrupt Enable Serial Input Data Ready Interrupt Enable Other Key Interrupt Enable Break Key Interrupt Enable
OS SHADOW: POKMSK (hex 10)
Use AND’s and OR's to change one bit in POKMSK without affecting the others. Store the desired value in both IRQEN and POKMSK.
VCOUNT (Vertical Counter)(D40B)
This address reads the Vertical TV Line Counter (8 most significant bits).
D7 D6 D5 D4 D3 D2 D1 D0 V8 V7 V6 V5 V4 V3 V2 V1 V0 V0 not read. Two line resolution supplied.
WSYNC (Wait for Horizontal Blank Synchronism – i.e. wait until start of next TV line.)(D40A)
D7 D6 D5 D4 D3 D2 D1 D0 Not used
This address sets a latch that pulls down on the RDY line to the microprocessor, causing it to wait until this latch is automatically reset by the beginning of horizontal blank. Display list interrupts may be delayed by 1 line if WSYNC is used. Used by OS keyboard click routine.
DMACTL (Direct Memory Access Control)(D400)
This address writes data into the DMA Control Register.
D7 D6 D5 D4 D3 D2 D1 D0 0 0 No Playfield DMA 0 1 Narrow Playfield DMA (128 Color Clocks) 1 0 Standard Playfield DMA (160 Color Clocks) 1 1 Wide Playfield DMA (192 Color Clocks) 1 Enable Missile DMA 1 Enable Player DMA 0 2 line P/M resolution 1 1 Line P/M resolution 1 Enable instruction fetch DMA Not used
See GRACTL. OS Shadow: SDMCTL (22F) default value hex 22
GRACTL (Graphics Control)(D01D)
This address writes data to the Graphic Control Register.
D7 D6 D5 D4 D3 D2 D1 D0 1 Enable Missile DMA to Missile Graphics Registers 1 Enable Player DMA to Player Graphics Registers. 1 Enable latches on TRIGO – TRIG3 inputs
(latches are cleared and TRIGO – TRIG3 act as normal inputs when this control bit is zero).Not used
DMA is enabled by setting bits in both DMACTL and GRACTL. Setting DMACTL only will result in cycles being stolen but no display will be generated.
CHACTL (Character Control)(D401)
This address writes data into the Character Control Register.
D7 D6 D5 D4 D3 D2 D1 D0 Character Blank (Blink) Flag (used for 40 Character Mode only). If bit 7 of character code is true this flag causes that character to blank. Blinking characters are produced by setting bit 7 of the characters to 1, then periodically changing D0 of CHACTL. Character Video Invert Flag (used for 40 Character Mode only). If bit 7 of character code is true this flag causes that character to be blue on white (if normal colors are white on blue). Character Vertical Reflect Bit. This bit is sampled at the beginning of each line of characters. If true it causes the line of characters to reflect (invert) vertically (for upside down characters). Not used
OS SHADOW: CHACT (2F3)
DLISTL( Display List Low )(D402)
This address writes data into the low byte of the Display List Counter.
D7 D6 D5 D4 D3 D2 D1 D0 7 6 5 4 3 2 1 0 Display List Counter Bit Position.
OS SHADOW: SDLSTL (hex 230)
DLISTH (Display List High)(D403)
High byte of the Display List Counter. This address writes data into the Display List Counter Bit Position.
D7 D6 D5 D4 D3 D2 D1 D0 15 14 13 12 11 12 11 10 Display List Counter Bit Position.
OS SHADOW: SDLSTH (HEX 231)
The Display List is a list of display instructions in memory. These instructions are addressed by the Display List Counter. Loading these registers defines the address of the beginning of the Display List (see sections I and II.)
Note: The top 6 bits are latches only and have no count capability, therefore the display list cannot cross a 1K byte memory boundary unless a Jump instruction is used.
DLISTL and DLISTH should be changed only during vertical blank or with DMA disabled. Otherwise, the screen may roll. Bit 7 of NMIEN most be set in order to receive display list interrupts.
CHBASE (Character Address Base Register)(D409)
This address writes data into the Character Address Base Register. The data specifies the most significant byte (MSB) of the address of the desired character set (see section II). Note that the last 1 or 2 bits are assumed to be 0.
40 Character Modes
D7 D6 D5 D4 D3 D2 D1 D0 CHBASE 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 Base
addressCharacter name Line
counter20 Character Modes
D7 D6 D5 D4 D3 D2 D1 D0 CHBASE 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 Base
addressCharacter name Line
counter
OS SHADOW: CHBAS (2F4)
PMBASE (Player-Missile Address Base Register D407)
This address writes data into the Player-Missile Address Base Register. The data specifies the MSB of the address of the player and missile DMA data (see section II).
1- line resolution
D7 D6 D5 D4 D3 D2 D1 D0 PMBASE 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 Base
addressPlayer
Missile
selectPlayer Missile
scan counter2- line resolution
D7 D6 D5 D4 D3 D2 D1 D0 PMBASE 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 Base
addressPlayer
Missile
selectPlayer Missile
scan counter
HSCROL (Horizontal Scroll Register)(D404)
This address writes data into the Horizontal Scroll Register. Only playfield is scrolled, not players and missiles.
D7 D6 D5 D4 D3 D2 D1 D0 0 to 15 color clock right shifts Don't care (written by OS NMI code)
The display is shifted to the right by the number of color clocks specified by HSCROL for each display list instruction that contains a 1 in its HSCROL Flag bit (bit 4 of instruction byte).
When horizontal scrolling is enabled, more bytes of data are needed. For a narrow playfield (see DMACTL bits 1 and 0) there should be the same number of bytes per line as for standard playfield with no scrolling. Similarly, for standard playfield use the same number of bytes as for the wide playfield. For wide playfield, there is no change in the number of bytes and background color is shifted in.
VSCROL (Vertical Scroll Register)(D405)
This address writes data into the Vertical Scroll Register.
8-line display modes:
D7 D6 D5 D4 D3 D2 D1 D0 0-7 Not used 16-line display modes:
D7 D6 D5 D4 D3 D2 D1 D0 0-15 Not used
The display is scrolled upward by the number of lines specified in the VSCROL register for each display list instruction that contains a 1 in its VSCROL Flag bit (bit 5 of instruction byte). The scrolled area will terminate with the first instruction having a zero in bit 5. (see section II for more details).
PRIOR (Priority)(D01B)
This address writes data into the Priority Control Register.
| D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 | Priority: (Mutually Exclusive). These bits select one of 4 types of priority. Objects with higher priority will appear to move in front of objects with lower priority. | ||||||
| 0 | 0 | 0 | 1 |
|
||||||||||
| 0 | 0 | 1 | 0 |
|
||||||||||
| 0 | 1 | 0 | 0 |
|
||||||||||
| 1 | 0 | 0 | 0 |
|
||||||||||
| NOTE: | ||||||||||||||
| The use of priority bits in a
"non-exclusive" mode (more than 1 bit true)
will result in objects (whose priorities conflict)
turning BLACK in the overlap region. EXAMPLE: PRIOR code = 1010. This will black P0 or P1 if they are over PF0 or PF1. It will also black P2 or P3 if they are over PF2 or PF3. The priority control register also controls the fifth player. The fifth player is the combination of all four missiles and shown as playfield 3 color-lum. However, there is no priority between playfields. Therefore, the fifth player would have no priority between playfields. |
||||||||||||||
| D4 | Fifth Player Enable | |||||||||||||
| This bit causes all missiles to assume the color of Playfield Type 3 (COLPF3). This allows missiles to be positioned together with a common color for use as a fifth player. | ||||||||||||||
| D5 | Multiple Color Player Enable | |||||||||||||
| This bit causes the logical "or" function
of the bits of the colors of Player 0 with Player 1 and
also of Player 2 with Player 3. This permits overlapping
the position of two players with a third player in the
overlapped region. The priority control register also controls playfield data interpretation from the ANTIC. There are four modes. They are: four color-lum (normal CTIA mode), 1 color - 16 lum (GTIA), 9 color-lum (GTIA), and 16 color- 1 lum (GTIA). |
||||||||||||||
| GTIA Playfield modes | ||||||||||||||
| 0 | 0 | Normal No GTIA mode ( CTIA operation) | ||||||||||||
| 0 | 1 | 1 color - 16 luminances mode | ||||||||||||
| 1 | 0 | 9 color-luminances mode | ||||||||||||
| 1 | 1 | 16 color- 1 luminance mode | ||||||||||||
OS SHADOW: GPRIOR (26F)
COLPFO – COLPF3 (Playfield Color)(D016, D017, D018, D019)
These addresses write data to the Playfield Color-Lum Registers.
D7 D6 D5 D4 D3 D2 D1 D0 (see COLBK for bit assignment)
OS SHADOWS: COLOR0 – 3 (2C4-2C7)
COLBK (Background Color)(D01A)
This address writes data to the Background Color-Lum Register.
D7 D6 D5 D4 D3 D2 D1 D0 X Not used 0 0 0 Zero luminance (black) 0 0 1 etc. 1 1 1 Max luminance (white) 0 0 0 0 Grey 0 0 0 1 Gold 0 0 1 0 Orange 0 0 1 1 Red-orange 0 1 0 0 Pink 0 1 0 1 Purple 0 1 1 0 Purple-Blue 0 1 1 1 Blue 1 0 0 0 Blue 1 0 0 1 Light Blue 1 0 1 0 Turquoise 1 0 1 1 Green-Blue 1 1 0 0 Green 1 1 0 1 Yellow-Green 1 1 1 0 Orange-Green 1 1 1 1 Light Orange
OS Shadow: COLOR4 (2C8)
DMACTL, GRACTL, PMBASE and PRIOR also affect players and missiles.
COLPM0 – COLPM3 (Player-Missile Color) (D012, D013, D014, D015)
These addresses write to the Player-Missile Color-Lum Registers. Missiles have the same color-lum as their player unless missiles are used as a 5th player (see bit 4 of PRIOR). A 5th player missile gets its color from COLPF3.
D7 D6 D5 D4 D3 D2 D1 D0 (See COLBK for bit assignments) OS SHADOWS: PCOLRO – 3 (2CO-2C3)
GRAPPO – GRAFP3 (Player Graphics Registers): (P0 D00D, P1 D00E, P2 D00F, P3 D010)
These addresses write data directly into the Player Graphics Registers, independent of DMA. If DMA is enabled then the graphics registers will be loaded automatically from the memory area specified by PMBASE(see page II.3).
D7 D6 D5 D4 D3 D2 D1 D0 (See COLBK for bit assignments) Left Right Player on TV Screen OS SHADOWS: PCOLRO – 3 (2CO-2C3)
GRAFM (Missile Graphic Gregisters) (D011)
This address writes data directly into the Missile Graphics Register, independent of DMA.
D7 D6 D5 D4 D3 D2 D1 D0 L R L R L R L R M3 M2 M1 M0
SIZEP0 – SIZEP3 (Player Size)(P0 D008, P1 D009, P2 D00A, P3 D00B)
These addresses write data into the Player Size Control Registers.
D7 D6 D5 D4 D3 D2 D1 D0 Horizontal Size Register (Player) 0 0 Normal Size (8 color clocks wide) 0 1 Twice Normal Size (16 color clocks wide) 1 0 Normal Size 1 1 4 Times Normal Size (32 color clocks wide) Not used
With normal size objects, each bit in the graphics register corresponds to one color clock. For larger objects, each bit is extended over more than one color clock.
SIZEM (Missile Size)(D00C)
This address writes data into the Missile Size Control Register.
| D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 | Horizontal Size Register (Missile) |
| Missile 0 | ||||||||
| 0 | 0 | Normal Size (2 color clocks wide) | ||||||
| 0 | 1 | Twice Normal Size (4 color clocks wide) | ||||||
| 1 | 0 | Normal Size | ||||||
| 1 | 1 | 4 Times Normal Size (8 color clocks wide) | ||||||
| As above, for Missile 1 | ||||||||
| As above, for Missile 2 | ||||||||
| As above, for Missile 3 | ||||||||
HPOSPO – HPOSP3 (Player Horizontal Position)(P0 D000, P1 D001, P2 D002, P3 D003)
These addresses write data into the Player Horizontal Position Register (see display diagram in section IV). The horizontal position value determines the color clock location of the left edge of the object. Hex 30 is the left edge of a standard width screen. Hex D0 is the right edge of a standard screen.
D7 D6 D5 D4 D3 D2 D1 D0
HPOSM0 - HPOSM3 (Missile Horizontal Position)(M0 D004, Ml D005, M2 D006, M3 D007)
These addresses write data into the Missile Horizontal Position Register (see HPOSPO description).
VDELAY (Vertical Delay)(D01C)
This address writes data into the Vertical Delay Register.
D7 D6 D5 D4 D3 D2 D1 D0 P3 P2 P1 P0 M3 M2 M1 M0
VDELAY is used to give one-line resolution in the vertical positioning of an object when the 2-line resolution display is enabled. Setting a bit in VDELAY to 1 moves the corresponding object down by one TV line.
If player-missile DMA is enabled then changing the vertical location of an object by more than one line is accomplished by moving bits around in the memory map. If DMA is disabled then the vertical location can be set up by assembly language code which stores data into the graphics registers at the desired line.
M0PF, M1PF, M2PF, M3PF (Missile to Playfield Collisions)(D000, D001, D002, D003)
These addresses read Missile to Playfield Collisions.
A 1-bit means that a collision has been detected since the last HITCLR.
D7 D6 D5 D4 D3 D2 D1 D0 3 2 1 0 Playfield type Not used (zero forced)
P0PF, P1PF, P2PF, P3PF (Player to Playfield Collisions)(D004, D005, D006, D007)
These addresses read Player to Playfield Collisions.
D7 D6 D5 D4 D3 D2 D1 D0 3 2 1 0 Playfield type Not used (zero forced)
MOPL, M1PL, M2PL, M3PL (Missile to Player Collision)(D008, D009, D00A, D00B)
These addresses read Missile to Player Collisions.
D7 D6 D5 D4 D3 D2 D1 D0 3 2 1 0 Player Number Not used (zero forced)
POPL, P1PL, P2PL, P3PL (Player to Player Collisions)(D00C, D00D, D00E, D00F)
These addresses read Player to Player Collisions.
D7 D6 D5 D4 D3 D2 D1 D0 3 2 1 0 Player Number Not used (zero forced)
(Player 0 against Player 0 is always a zero). Etc.
HITCLR (Collision, "HIT" clear) (D01E)
This write address clears all collision bits described above.
D7 D6 D5 D4 D3 D2 D1 D0 Not used
AUDCTL (Audio Control)(D208)
This address writes data into the Audio Mode Control Register. (Also see SKCTL two-tone bit 3 and notes).
D7 D6 D5 D4 D3 D2 D1 D0 Change Normal 64 KHZ frequency, into 15 KHZ. Insert Hi Pass Pilter in Channel 2, clocked by Channel 4. Insert Hi Pass Filter in Channel 1, clocked by Channel 3. (See section II.) Clock Channel 4 with Channel 3, instead of 64 KHz (16 BIT). Clock Channel 2 with Channel 1, instead of 64 KHz (16 BIT). Clock Channel 3 with 1.79 MHz, instead of 64 KHz. Clock Channel 1 with 1.79 MHz, instead of 64 KHz. Change 17 bit poly into a 9 bit below poly.
Exact Frequencies
The frequencies given above are approximate. The Exact Frequency (Fin) that clocks the divide by N counters is given below (NTSC only, PAL different).
FIN Approximate FIN Exact NTSC PAL 1.79 MHz 1.78979 MHz – Use modified formula for Fout 64 kHz 63.9210 kHz – Use normal formula for Fout 15 kHz 15.6999 kHz
The Normal Formula for output frequency is:
Fout = Fin / 2N
Where N The binary number in the frequency register (AUDF), plus 1 (N=AUDF+1). The MODIFIED FORMULA should be used when Fin = 1.79 MHZ and a more exact result is desired:
Fout = Fin / 2(AUDF + M)
| Where: | M = 4 if 8 bit counter (AUDCTL bit 3 or 4 = 0) |
| M = 7 if 16 bit counter (AUDCTL bit 3 or 4 = 1) |
AUDF1, AUDF2, AUDF3, AUDF4 (Audio Frequency) (D200, D202, D204, D206)
These addresses write data into each of the four Audio Frequency Control Registers. Each register controls a divide by "N" counter.
D7 D6 D5 D4 D3 D2 D1 D0 "N" 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 etc. 1 1 1 1 1 1 1 1 256
Note: "N" is one greater than the binary number in Audio Frequency Register AUDF(X).
AUDC1, AUDC2, AUDC3, AUDC4 (Audio Channel Control)(D201, D203, D205, D207)
These addresses write data into each of the four Audio Control Registers. Each Register controls the noise content and volume of the corresponding Audio Channel.
Noise Content or Distortion, and Volume
D7 D6 D5 D4 D3 D2 D1 D0 HEX volume: 0 0 0 0 0 Lowest Volume (Off) 8 1 0 0 0 Half Volume etc F 1 1 1 1 Highest Volume Distortion:
Divisor "N" set by audio frequency register.0 0 0 0 0 17 Bit poly - 5 Bit poly - N 2 0 0 1 0 5 Bit poly - N - 2 4 0 1 0 0 4 Bit poly - 5 Bit poly - N 6 0 1 1 0 5 Bit poly - N - 2 8 1 0 0 0 17 Bit poly - N A 1 0 1 0 Pure Tone - N - 2 C 1 1 0 0 4 Bit poly - N 1 X X X 1 Force Output Volume only
PITCH VALUES FOR THE MUSICAL NOTES - AUDCTL=0, AUDC = hex AX
| AUDF | |||
| Hex | Dec | ||
| HIGH NOTES | C | 1D | 29 |
| B | 1F | 31 | |
| A# or Bb | 21 | 33 | |
| A | 23 | 35 | |
| G# or Ab | 25 | 37 | |
| G | 28 | 40 | |
| F# or Gb | 2A | 42 | |
| F | 2D | 45 | |
| E | 2F | 47 | |
| D# or Eb | 32 | 50 | |
| D | 35 | 53 | |
| C# or Db | 39 | 57 | |
| C | 3C | 60 | |
| B | 40 | 64 | |
| A# or Bb | 44 | 68 | |
| A | 48 | 72 | |
| G# or Ab | 4C | 76 | |
| G | 51 | 81 | |
| F# or Gb | 55 | 85 | |
| F | 5B | 91 | |
| E | 60 | 96 | |
| D# or Eb | 66 | 102 | |
| D | 6C | 108 | |
| C# or Db | 72 | 114 | |
| MIDDLE C | C | 79 | 121 |
| LOW NOTES | B | 80 | 128 |
| A# or Bb | 88 | 136 | |
| A | 90 | 144 | |
| G# or Ab | 99 | 153 | |
| G | A2 | 162 | |
| F# or Gb | AD | 173 | |
| F | B6 | 182 | |
| E | C1 | 193 | |
| D# or Eb | CC | 204 | |
| D | D9 | 217 | |
| C# or Db | E6 | 230 | |
| C | F3 | 243 | |
STIMER (Start Timer)(D209)
This write address resets all audio frequency dividers to their "AUDF" value. These dividers generate timer interrupts when they count down to zero (if enabled by IRQEN). (also see IRQST)
D7 D6 D5 D4 D3 D2 D1 D0 not used
RANDOM (Random Number Generator)(D20A)
This address reads the high order 8 bits of a 17 bit polynomial counter (9 bit, if bit 7 of AUDCTL 1).
D7 D6 D5 D4 D3 D2 D1 D0
CONSOL (Console Switch Port)(D01F)
This address reads or writes data from the console switches
and indicators. (Set to 8 by OS Vertical Blank code.)
Hex 08 should be written to this address before reading the
switches.
Ones written will pull down on the switch line.
| D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 | |
| Game Start | ||||||||
| Game Select | ||||||||
| Option Select | ||||||||
| Loudspeaker | ||||||||
| Not Used (zero forced) | ||||||||
– 0 means switch pressed.
– should be held at 1 except when writing 0 momentarily. OS
writes a 1 during vertical blank'.
KBCODE (Keyboard Code)(D209)
This address reads the Keyboard Code, and is usually read in response to a Keyboard Interrupt (IRQ and bits 6 or 7 of IRQST). See IRQEN for information on enabling keyboard interrupts. See SKCTL bits 1 and 0 for key scan and debounce enable.
D7 D6 D5 D4 D3 D2 D1 D0 Key code Shift Key Control Key
Read by OS into shadow CH when key is hit. The OS has a get character function which converts the keycode to ATASCII (Atari ASCII).
KEYCODE TO ATASCII CONVERSION
|
|
** = special handling
SKCTL (Serial Port control)(D20F)
This address writes data into the register that controls the configuration of the serial port, and also the Reset Pot Scan and Keyboard Enable.
| D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 | (Bits are normally zero and perform the functions shown below when true.) |
| 0 | 0 | D0-D1 (Both Zero) Initialize (State used for testing and initializing chip) ** | ||||||
| 1 | Enable Debounce (Enables Keyboard Debounce circuits) | |||||||
| 1 | Enable Key Scan (Enables Keyboard Scanning circuit) | |||||||
| Fast Pot (Fast Pot Scan. The Pot Scan Counter completes its sequence in two TV line times instead of one frame time. The capacitor dump transistors are completely disabled.) | ||||||||
| Two Tone (Serial output transmitted as two tone signal instead of logic true/false.) | ||||||||
| Serial Port Mode Control (see mode chart at end of Serial port description, page II.34). | ||||||||
| Force Break (force serial output to zero (space))* | ||||||||
OS SHADOW: SSKCTL (hex 232)
The OS enables key scan and debounce and may change the other bits for different I/0 operations. In particular, an aborted cassette operation may leave the two tone bit in the true state, causing undesirable audio signals. This may be corrected by writing hex 13 to both SKCTL and SSKCTL after doing I/0 and/or before modifying the audio registers.
| * NOTE: | When powered on, serial port output may stay low even if this bit is cleared. To get S.P. high (mark), send a byte out (recommend 00 or FF). |
| **NOTE: | There is no original power on state. Pokey has no reset pin. |
SKSTAT (Serial Port-Keyboard Status)(D20F)
This address reads the status register giving information about the serial port and keyboard.
| D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 | (Bits are normally true and provide the following information when zero.) | |
| 1 | Not Used (Logic True) | ||||||||
| 0 | Serial Input Shift Register Busy | ||||||||
| 0 | Last Key is Still Depressed | (D5 and D6 are set to zero when new data and same bit of IRQST is zero) | |||||||
| 0 | Shift Key Depressed | ||||||||
| 0 | Direct from Serial Input Port | Latches must be reset to 1 by SKRES | |||||||
| 0 | Keyboard Over-run | ||||||||
| 0 | Serial Data Input Over-run | ||||||||
| 0 | Serial Data Input Frame Error | ||||||||
SKRES (Reset above Status Register)(D20A)
This write address resets bits 7, 6, and 5 of the Serial Port-Keyboard Status Register to 1.
D7 D6 D5 D4 D3 D2 D1 D0 not used
SERIN (Serial Input Data)(D20D)
This address reads the 8 bit parallel holding register that is loaded when a full byte of serial input data has been received. This address is usually read in response to a serial data in interrupt (IRQ and bit 5 of IRQST). Also see IRQEN.
D7 D6 D5 D4 D3 D2 D1 D0
Serial I/0 Port Connector Pinout
2 4 6 8 10 12 o o o o o o o o o o o o o 1 3 5 7 9 11 13
1. Clock Input 2. Clock Output 3. Data Input 4. Ground 5. Data Output 6. Ground 7. !Command 8. Motor Control 9. !Proceed 10. +5V/Ready (not on 1200XL) 11. Audio Input 12. +12V (400,800 only. 1400XL/1450XLD?) 13. !Interrupt
See serial port description in OS manual for more details.
SEROUT (Serial Output Data)(D20D)
This address writes to the 8 bit parallel holding register that is transferred to the output serial shift register when a full byte of serial output data has been transmitted. This address is usually written in response to a serial data out attempt (IRQ and bit 4 of IRQST).
D7 D6 D5 D4 D3 D2 D1 D0
PORTA (Port A)(D300)
This address reads or writes data from Player 0 and Player 1 controller Jacks if bit 2 of PACTL is true. This address writes to the direction control register if bit 2 of PACTL is zero. I/0 for both ports (A and B) goes through a 6520/6820.
Data Register-Addressed if bit 2 of PACTL is 1.
Joystick Operation
D7 D6 D5 D4 D3 D2 D1 D0 0 = Switch pressed
1 = Switch not pressedForward Stick 0
(Jack 1)Backward Left Right Forward Stick 1
(Jack 2)Backward Left Right
Paddle Operation
D7 D6 D5 D4 D3 D2 D1 D0 0 = Switch pressed
1 = Switch not pressedForward Stick 0
(Jack 1)Backward Left Right Forward Stick 1
(Jack 2)Backward Left Right
Keyboard Controller Operation
D7 D6 D5 D4 D3 D2 D1 D0 0 = Switch pressed
1 = Switch not pressedTop row Jack 1 2nd row 3rd row 4th row Top row Jack 2 2nd row 3rd row 4th row
Direction Control Register-Addressed if bit 2 of PBCTL is 0
D7 D6 D5 D4 D3 D2 D1 D0
Each bit corresponds to a Jack pin
0 = input
1 = output
OS SHADOWS: STICK0 (hex 278), STICK1 (279), PTRIGO-3 (27C-27F)