II.C· SERIAL PORT

The serial port consists of a serial data output (transmission) line, a serial data input (receiver) line, a serial output clock line, a bi-directional serial data clock line, and other miscellaneous control lines described in the Operating System Manual. Data is transmitted and received as 8 bits of serial data preceded by a logic zero start bit, and succeeded by a logic true stop bit. Input and output clocks are equal to the baud (bit) rate, not 16 times baud rate. Transmitted data changes when the output clock goes true. Received data is sampled when the input clock goes to zero.

Serial Output

The transmission sequence begins when the processor writes 8 bits of parallel data into the serial output register (SEROUT)(see audio and serial port block diagram). When any previous data byte transmission is finished the hardware will automatically transfer new data from (SEROUT) to the output shift register, interrupt the processor to indicate an empty (SEROUT) register (ready to be reloaded with the next byte of data), and automatically serially transmit the shift register contents with start-stop bits attached. If the processor responds to the interrupt, and reloads SEROUT before the shift register is completely transmitted, the serial transmission will be smooth and continuous.

Output data is normally transmitted as logic levels (+4V = true 0V = False). Data can also be transmitted as two-tone information. This mode is selected by bit 3 of SKCTL. In this mode audio channel 1 is transmitted in place of logic true, and audio channel 2 in place of logic zero. Channel 2 must be the lover tone of the tone pair.

The processor can force the data output line to zero (or to audio channel 2, if in two tone mode) by setting bit 7 of SKCTL. This is required to force a break (10 zeros) code transmission.

Serial Output Clock

The serial output data always changes when the serial output clock goes true. The clock then returns to zero in the centre of the output data bit time.

The baud (bit) rate of the data and clock is determined by audio channel 4 audio channel 2, or by the input clock, depending on the serial mode selected by bits 4, 5, and 6 of SKCTL. (See chart at end of this section.)

Serial Input

The receiving sequence begins when the hardware has received a complete 8-bit serial data word plus start and stop bits. This data is automatically transferred to the 8 bit parallel input register (SERIN), and the processor is interrupted to indicate an input data byte ready to read in SERIN. The processor must respond to this interrupt, and read SERIN, before the next input data word reception is complete, otherwise an input data "over-run" will occur. This over-run will be indicated by bit 5 of SKSTAT (if bit 5 of IRQST is not RESET (true) before next input complete), and means input data has been lost. This bit should be tested whenever SERIN is read. Bit 7 of SKSTAT should also be tested to detect frame errors caused by extra (or missing) data bits.

Direct Serial Input

The serial data input line can be read directly by the microprocessor if desired, ignoring the shift register, by reading bit 4 of SKSTAT.

Bi-directional Clock

This clock line is used to either receive a clock from an external clock source for clocking transmitted or received data, or is used to supply a clock to external devices indicating the transmit or reception rate. This clock line direction is determined by the serial mode selected by bits 4, 5, and 6 of SKCTL. (See mode chart at the end of this section.) Transmitted data changes on the rising edge of this clock. Received data is sampled on the trailing edge of this clock.

Asynchronous Serial Input

Unclocked serial data (at an approximately known (+5%) rate) can be received in the asynchronous modes. The receive (input) shift register is clocked by audio channel 4. Channels 3 and 4 should be used together (AUDCTL bit 3 = 1) for increased resolution.

In asynchronous modes, channels 3 and 4 are reset by each start bit at the beginning of each serial data byte. This allows the serial data rate to be slightly different from the rate set by channels 3 and 4.

Serial Mode Control

There are 6 useful modes (of the possible 8) controlled by bits 4, 5, and 6 of SKCTL. These are described on the next page.

Note that two tone output (bit 3 of SKCTL) may be used in any of these modes except for the bottom pair. This is because channel 2 is used to set the output transmit rate and is therefore not available for one of the two tones.

Note that the output clock rate is identical to the output data rate.

Serial Mode Control (see also register description SKCTL)

D7 D6 D5 D4 D3 D2 D1 D0 SKCTL REGISTER
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  Pot scan and keyboard CTRL
A = asynchronous
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V
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V
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V
  Out
rate
Out
Clk
In
rate
Bidir
clock
Comments
  0 0 0 --------> ext ext ext ext
input
Transmit & Receive rates set by external clock.
Also internal clock phase reset to zero.
0 0 1 --------> ext ch.4
A
ext
input
ext
input
Transmit rate set by external clock.
Receive asynch. (ch. 4)
(CH3 and CH4)
0 1 0 --------> ch.4 ch.4 ch.4 ch.4
output
Transmit & Receive rates set by Chan. 4.
Chan. 4 output on Bi-Directional clock line.
0 1 1 --------> ch.4
A
ch.4
A
ch.4
A
input Not Useful
1 0 0 --------> ch.4 ch.4 ch.4 ext
input
Transmit Rate Set by Chan. 4
Receive Rate set by External Clock.
1 0 1 --------> ch.4
A
ch.4
A
ch.4
A
input Not Useful
1 1 0 --------> ch.2 ch.2 ch.2 ch.4
ouput
Transmit rate set by chan. 2
Receive rate set by chan. 4
Chan.4 out on Bi-Direct. Clock line.
1 1 1 --------> ch.2 ch.2 ch.4
A
  Transmit Rate set by Chan.
Receive async. (chan 3 & 4) )
Bi-Dir Clock not used (Tri-state action)

Two tone (bit 3) not useable in these modes.