VDU-K Interak 1 VDU Interface
The VDU-K provides a high-quality display on a standard 625-line TV set, via its on-board wide bandwidth UHF modulator, or if desired a composite video signal is independently available to drive a TV monitor. The user can choose to have either black characters on a white background, or white characters on a black background, according to his or her personal preference.
The VDU-K appears to the computer as 1K of RAM, starting at any chosen 1K boundary, selected by DIL switches. However in fact only the first 0.75K of the VDU RAM is displayable, and the last 0.25K is available to the user (this can be quite useful in a very small system w.hich involves a VDU-K, as there is sometimes no need for a separate RAM card). It should be noted that it is not possible to run programs in the video RAM, the timing restrictions are such that it can only be used as read/write memory.
The 7-bit ASCII code is used as the basis for the character definition, for example a "41" (hexadecimal notation) written to the first location in the VDU RAM would result in a letter "A" being displayed in the top left-hand corner of the VDU screen, "42" would be "B", and so on. As the entire character generator set is held in EPROM, any desired sequence or font of characters can be programmed. The total screen displays as 256 dots across x 240 dots down, so for special applications graphics characters having an equivalent resolution of 61,440 dots per screen can be programmed into the EPROM character generator. Examples of special dedicated applications are chess pieces, and pipes and steam valves etc. to give a..very inexpensive "mimic" diagram for process control and the like.
The standard 2716 EPROM pre-programmed character generator provides 128 characters including all of the printable ASCII characters, upper-and lower-case letters, with "descenders" where appropriate. A 5x7 matrix is used for the majority of the characters, and the matrix is placed within the 8x10 character cell so that these inverted video characters do not "fall out" of the cell, and thus remain very readable. The non-printing ASCII characters (carriage-return, line-feed and so on) make up the remainder of the standard 2716 character generator. Line-drawing and "pixel" characters (quarter character squares) are displayed for most of the non-printing codes, and there are a few graphics characters in the remaining space.
If the 7-bit ASCII code is presented to the VDU-K in a byte with the high bit set, the displayed character will appear in inverse video, i,.e. black will be white, and vice versa, for that particular character. An alternative option is to let the high bit select a whole new character generator EPROM, containing a further 128 pre-programmed characters, making 256 in all, The extra characters are normally contained in a second 2716 EPROM, but the pair of EPROMs can be replaced if desired by a single type 2532 or 2732.
The second set of characters if used is called the "Applications" character set, as they will depend to what application the VDU-K is being put. For an amusement arcade type of game the Applications EPROM could contain assorted space invaders and the like, whereas for a computer aided circuit design application the EPROM could contain transistor, resistor, logic gate etc. symbols.
Any of the dots in the 8x10 character cell can be programmed into the EPROM character generator, and adjacent cells touch on the screen, so that the character set designer has a fairly free hand.
The outstanding feature of the VDU-K is that there are no restrictions placed on the timing of CPU reads and writes. A Z80A operating at 4 MHz can read from or write to a location on the screen at any time, without causing any disturbance ("snow") whatever on the display. "Wait" states are not required, and in fact are detrimental since they prolong the CPU access long enough to deprive the VDU of its correct data and so cause "snow" on the screen. The CPU can be operated at a lower speed, but the anti-snow feature of the VDU-K will not be so effective.
A television sync. waveform has to be fairly complex if it is to meet the required specification. For example there should be five half line equalising pulses at the beginning and end of each frame, and the line sync. should be kept going during the frame sync. time. It is very rare even for modern computers to comply with these latter requirements; most often they discontinue the line pulses during the frame sync. time, and hope that the good natured television set line timebase can regain line synchronisation in time to avoid spoiling the display. If you look at the top few lines of the television output of many computers you will see what a forlorn hope this is, as there is often visible "pulling” at the top of the display.
As a television set has a fairly short persistence phosphor, better results are often obtained by choosing a "non-interlaced" display, since this refreshes individual picture elements at a 50 Hz rate rather than the 25 Hz rate of a fully interlaced display. Particularly when viewed from a metre or less, there is much reduced flicker with a non-interlaced display. The VDU-K has an alterable link (or switch setting if a switch is fitted) so that the user can select whichever he prefers.
The necessary complication of the sync. waveform circuit has been satisfied in a unique manner on the VDU-K. Instead of the several LS TTL packages that would have been required to generate the proper "no compromises" interlaced/non-interlaced sync. timing, a dedicated Z80A has been used. Although no work has been carried out on this question, it is possible that it would be fairly easy to modify the control program to suit other TV standards, e.g. 525 lines instead of 625.
Because of the good number of internal registers in the Z80A, no external RAM is needed in this application, and it turns out that the use of the Z80A for sync. generation uses less space than the alternative solutions, and as a bonus is cheaper.
The number of characters across the sc.reen is limited by the bandwidth of the television receiver. The number chosen (32) was selected for several reasons: to be compatible with earlier systems (e.g VDU-A,B,G), and to enable much of the software for the Sinclair ZX-81 (which uses the same format) to be converted easily by users. The number 32 is the round figure "20" in hexadecimal, which makes the task of handling fast motion on the screen (one of the main. applications of a "no snow" VDU) much easier to program. With a fairly large character cell like this a sizeable character block results if adjacent cells are joined together. This makes games such as "Space Invaders" much more enjoyable than if they are played with very small, cramped characters. Also the good size character is very legible especially at a distance, for example if displaying announcements (e.g. airport announcements, betting shop results etc.) on a television set. The final benefit attached to the number of characters chosen is the fact that the character cell is near enough square. Apart from improving legibility of alphanumeric characters, this means that 45 degree lines plotted using the pixel characters are very close to the correct angle, and a circle is very close indeed to being circular. (Unless you are experienced with computers you,will be quite surprised to find how many circles plotted even on quite expensive machines are not circular at all.)
All of the components used are readily available, and the 27 integrated circuits used are all laid out the same way round, which makes the card very straightforward to construct and test. Wherever possible signal tracks which have to pass between the legs of ICs are taken on the A-side so that they can be inspected in case of trouble. (Less considerate designers take them on the B-side where any shorts will be hidden under the IC sockets!) Plated-through hole construction is provided, and a solder resist mask on the A-side, sometimes also on the B-side.
Although all of the signals are taken via the A-side of the edge connector (which is gold-plated) and a gold-plated edge connector is also provided on the B-side.
The kit of components, which is sold separately to the PCB itself, includes 18 resistors, 1 SIL resistor pack, 1 variable resistor, 17 capacitors, 2 diodes, 1 transistor, 1 12.0 MHz crystal, 26 integrated circuits (including the standard character generator, and sync. pulse generator), 28 integrated circuit sockets (including sockets for the optional DIL switch and 2nd character generator), and some wiring pins. A 1" metal card front and some connectors and option switches are recommended but are not included in the kit to keep the basic cost down for those working to limited budgets. Also note that the wide bandwidth modulator (Type UM1233 E36) should be purchased separately, It has not been included because an increasing number of users. now have Video Monitors, and/or can salvage a modulator from a disused computer, e.g. ZX-80.
For the convenience of those users who may already have some of the parts required, all of the components are available separately! EPROMs already programmed with the timing program and a standard character generator set can be supplied at modest cost.
The VDU-K fits into an Interak 1 computer and provides the means for the user to view output data from the computer. However the VDU-K is also described as an "Applications" VDU, in that it can provide the visual output for numerous applications to which a computer may be put. For example a dedicated chess-playing computer could use the VDU-K with a pre-programmed set of chess pieces, or other applications may, be a set of named pictures to help children in their reading, or a set of electronic components for electronic circuit design, or graphic displays of animals for computer controlled feeding etc. in animal husbandry. Many of the applications to which the VDU-K can be put,have been known for many years but it has been too expensive to devote a whole computer to a fairly simple application. Extremely low-cost displays are possible because the VDU-K is designed to give excellent results on a standard TV receiver.
For some applications more than one display screen is required and the VDU-K can satisfy these by a simple adjustment to the address selection links or switches to allow more than one card to be plugged into the same system.
Although the VDU-K is designed to fit into the Interak 1 computer it is a standard size (4.5 x 8 inch) card which can be incorporated into other computer systems. To these computers the VDU-K card simply looks like 1K of RAM (read/write) memory, the first 768 locations of which are displayable on the TV screen. In a manner of speaking the TV screen is like a "window" through which the contents of a portion of the computer memory, can be examined. If the computer program wants to display a message or picture for the user to see it simply writes the codes for the appropriate data into this area of RAM, and they are displayed on the screen by the VDU-K.
For alphanumeric data such as the letters of the alphabet, numbers, and punctuation, a suitable well known code exists, the American Standard Code for Information Interchange, or "ASCII" for short. In this code the capital letters of the alphabet, A, B, C, etc. (for example) are represented by the computer codes 41H, 42H, 43H, etc, (the suffix "H" means that these numbers are the hexadecimal numbers often used in computer work, rather than conventional decimal numbers).
The computer reads or writes the data stored on the VDU-K card in the form of an eight-bit byte, at one of 64K different locations or addresses (64K = 64 x 1024 since 1K = 1024; do not confuse this with 1k which = 1000). The total memory on the VDU-K card comprises 1K such locations, although only the first three quarters of them are visible on the screen, The 1K memory on the VDU-K card can be sited at any one of 64 different locations (known as 1K boundaries) within a 64K system, and can be selected by altering the position of six wire links or DIL switches (there are 64 different ar,range,ments of these six selection links or switches since they each can have two positions and 2^6 = 64).
As the data are in the form of eight bit bytes there are a total of 2^8 = 256 possible different characters. These are held in two 2K EPROMs, U24 which holds the first 128 characters, and U23 which holds the next 128. As EPROMs get cheaper and cheaper it may happen that the 4K type 2532 or 2732 may be more economic than a pair of 2K types. The card is laid out so that a single 4K EPROM can be used in place of the pair of 2K ones. As the 2532 and 2732 are not pin compatible a jumper area (P5) has been provided so that either may be fitted.
In normal circumstances only one 2K EPROM is fitted at first. The ASCII code is a seven bit code and so there are only 2^7 = 128 possible different characters in that set, in fact there are less because many of the ASCII codes are "non printable" e.g. carriage return, delete, back-space etc. The standard 2K character generator EPROM for this board contains mostly the printable ASCII codes, but some special characters have been included as well, especially for the "non printable" codes. When only this single character generator is installed the remaining 128 codes are not wasted. Instead a switch option is selected so that the second 128 set of characters are the same as the first but presented in reverse video, i.e. white appears as black and vice versa. The use of reverse video is useful for dramatic warnings and headings on a displayed screen, and is also often used to indicate the position of a screen cursor which would otherwise obliterate any character in whose position it was resting.
If the standard character generator is installed then the second character generator which may be fitted to give 128 totally different characters (rather than simply the reverse video version of the first 128), is described as the "Applications Characters" EPROM. It is called this since the contents of this generator will depend on the precise application to which the VDU-K is being put. Of course "Applications" characters could be put in the first EPROM as well, but this is thought of as being unusual on the grounds that there are many applications which require the use of alphanumeric characters for messages, labels, etc. and it suits everybody’s convenience if these standard characters are to be found in a standard position.
A design for a "Programmable Character Generator" is now available, and the production of a suitable printed circuit board is under consideration. In the design a RAM-based character generator is connected via ribbon cable to the "Applications Characters" EPROM socket. This provides 128 characters which can be defined and redefined as a program runs, and can often give the illusion of high resolution graphics.
A further application for the VDU-K is to act as a test-bed for other screen formats, for example usable results with a 64 character line have been reported. This is not supported by the designers of the card however because of the reappearance of the "snow" effect.
Although the card has been designed with a television receiver in mind for economy, components have been included so that a T V. Video Monitor (composite video) can be used as well if desired. An on-board modulator is used for the standard T V. receiver output. The modulator used gives first-class results, but suffers from the disadvantage that it requires a non standard video signal, so this is produced on the card in addition to the "normal" video signal.
A unique microprocessor controlled TV sync. generator circuit has been adopted, and as a result it has been possible to provide a switch option to choose between an interlaced and a non-interlaced display.
Full buffering has been included so that no more than one input connection is made to any of the edge connector lines. Operation with a Z80A at a full 4 MHz without "wait" states is possible (and recommended for no "snow"), but the card can be used with certain other microprocessors. It is very simple to use in that it requires only an address bus (with memory request if appropriate), a data bus, and the read and write control strobes. The Z80A refresh signal has been included however to ensure that the VDU-K does not respond to a dynamic RAM refresh address. Power requirements are all met by a single +5V supply.
The mechanism whereby the data are converted to a form where they can be displayed on a TV screen is discussed in detail later in this Manual, but a general description is as follows: The eight bit bytes representing the characters which are to be displayed are stored in the RAM on this card. This RAM is known as the "video" RAM. A set of multiplexers connect the RAM addresses to the microprocessor bus should the microprocessor require to read from or write to the video RAM, but most of the time the multiplexers connect a counter chain (derived from a crystal oscillator) which is cycling round continuously during the time a picture is being displayed. As the counters cycle they present first one address, then the next, and the next, and so on, in turn to the video RAM. As a result the data contained in each of the displayable RAM locations are output byte at a time in sequence by the video RAM. If for example the letters A, B, C, were to be displayed the codes would be (for the standard ASCII character generator), 41H, 42H, 43H, one after another. These output data codes are presented as addresses to the character generator EPROM which is programmed with the pattern of 0's and 1's which are to be transmitted to the TV screen. Since a TV picture is made up of individual dots the eight bits of character information data from the EPROM are loaded into a shift register and clocked out by the "dot clock" a dot at a time while the EPROM is producing the pattern for the next character.
Each character such as the letter A, for example, is made up from a number of horizontal rows of dots arranged vertically above one another. In this case there are ten such rows or "picture lines" for each character. This means that the EPROM character generator must be accessed as described above ten times for each character displayed. This is done by having a picture line counter which provides an additional address to the EPROM. Only after ten picture lines are dispayed does the count proceed to get the next set of characters from the video RAM.
The output of the shift register is added to, and synchronised with, the timing information from the TV sync generator to provide two composite video signals, one of which can drive a TV Monitor, the other of which can drive an ordinary TV / receiver, via an on board modulator.
This concludes the general description of the VDU-K circuit.
There are two positions on the card where DIL switches may be fitted, Sl and S2. DIL switches are not supplied in the standard kit of parts as they are fairly expensive and many users will prefer to make other arrangements. However DIL sockets for both Sl and S2 are supplied. It will be assumed for convenience of writing that switches have been fitted, but there is no reason why the connections could not be made some other way, for example DIL pin headers, or wire links, perhaps on the track side of the board.
It is in fact recommended that no switch or links be fitted on the board in position S1, but the type of DIL switch which could be used here is DPDT (double-pole, double throw); great care should be exercised if the more common type of DIL switch is used instead (i e. 2 x SPDT) as it is quite easy to short one of the signals to ground, possibly with damaging consequences. The recommended method is to use instead the two sets of 3-pole connection pins Pl and P2, to connect a front panel mounted DPDT switch. Sheet 6 of the circuit diagram in section 5 of this Manual shows S1 and the alternative connections.
The purpose of the switch is to permit the user to have control over the function of the eighth bit of the VDU data. If a single character generator is in use, giving a standard set of 128 characters, then the eighth bit can be used to provide a duplicate set, but in reverse video. The setting of the switch is marked on the diagram as "REV". So for example if this setting was chosen and the data 2A (hex.) and AA (hex.) were written to the VDU RAM then 2A would normally result in a white asterisk (*) being displayed on a black background, whereas AA would result in the same character being displayed as black on white. This is because AA has the same seven low bits as 2A, but has the eighth bit set to "1".
If a second character generator (the "applications" character generator) is in use then the switch should be set to the "ALT" position if it is wished that the eighth bit select one of the alternative 128 characters. Taking the same example as before, 2A would be the same asterisk in normal non-reversed video, but this time AA would be whatever character had been programmed into the second EPROM, e.g. a chess-piece, or some other graphics symbol.
It might be thought that if a second character generator is in use then the front panel switch described is redundant. This is not the case, because many programs rely on the eighth bit being simply a reverse-video control bit. One notable program which needs this is ZYMON for its cursor, and it is also often used in Text Editing programs say to highlight a block of text before it is moved or deleted. It is suggested that the switch be left normally in the "REV" position, and only moved to "ALT" when it is desired to use the characters in the Applications EPROM (if fitted).
A 16-pin socket is provided for S2, which should be an 8 x SPST type if a DIL switch is used. We can therefore refer to eight switches S2a to S2h; S2a connecting pins 1 and 16 of the socket, if the pins are counted in the same way as for a 16-pin IC.
The first six switches S2a-S2f choose on which of the 64 possible 1K boundaries the VDU-K memory is to be located. S2a is the MSD (most significant digit) and corresponds to the chosen state of address bus line AB15; the other switches continue in sequence until S2f is reached, which corresponds to AB10. Note that due to the fact EX-OR gates are used to select the chosen address (see circuit diagram Sheet 3), the complement of the address should be sat on the switches, i.e. for an address with a "1" on a given line, the corresponding switch should be set to "0", by turning that switch ON. For example for use in an Interak 1 system with a ZYMON 2 monitor, the VDU RAM has to begin at address FOOO hex. The most significant bits of this number in binary notation are 1-1-1-1-0-0, and so the required settings for S2a to S2f are ON-ON-ON-ON-OFF-OFF respectively.
The next switch, S2g, is used to alter the VDU-K circuit to suit some types of microprocessor other than the Z80A-CPU, notably those types which do not provide an NMREQ signal like that of the Z80A-CPU. By closing this switch for this type of microprocessor, e.g. INS-8060, SC/MP, it is sometimes possible to reduce the time of the CPU access so that the "no snow" feature of the VDU-K is retained. For Z80A use in the Interak 1 system S2g should be left OFF.
The final switch is S2h. This is to be found on circuit diagram Sheet 2. It alters address line A9 on the timing generator EPROM U2, and so selects an alternative timing program, if one is provided in the EPROM. In the case of the first standard EPROM supplied for U2, S2h in the OFF position selects a timing program for a non-interlaced display, and S2h in the ON position selects a timing program for an interlaced display. Most people seem to prefer the non-interlaced display once they have seen both, and so they will leave S2h OFF.
Summary of S2 Switch Positions for Interak 1 Use:
Set S2a-h ON-ON-ON-ON-OFF-OFF-OFF-OFF respectively.
S3 is a further optional switch or link. If a switch is used it should be a SPST type, mounted preferably on the front panel. The switch is connected between pins 1 and 2 of pin assembly P4. It is shown on Sheet 7 of the circuit diagram in Section 5. Normally the switch is closed, and the normal characters appear as white on a black background, reverse video characters being black on white. At all times with S3 closed the top bottom and side margins on the screen are black. The function of S3 open is to "Reverse All", i.e. the top bottom and side margins and the normal screen are all white, and normal characters now appear as black on a white background, with reverse video characters now being white on black. It is suggested that consideration be given most seriously to choosing this latter option. In many applications, particularly those where the screen is viewed by people who do not usually use computers, the "Reverse All" option will often meet with wider acceptance. One reason is that people are accustomed to reading the printed word as black on white, and another is that the dots which make up the characters are not dots at all when they are black; they therefore appear to make more attractive "joined up" characters.
It is worth-while having a front panel switch because the white background can become a bit overpowering when viewed for long periods, and the hardened computer user will usually find the black background more restful on the eye.
There is space on the card for the fitting of a UHF modulator type UM1233 E36, to provide an output suitable for connecting to the aerial socket of an unmodified television receiver. Even though many users may have access to a video monitor, it is suggested that unless funds are really short the UHF modulator always be fitted. This is because in.the event of a breakdown to the UHF monitor, work with the computer can still proceed if a TV set can be found. This is a similar recommendation to that in the motoring world where motorists are advised to carry and maintain a spare tyre, and of course this advice may be disregarded. The connection to the modulator can be taken directly from the phono socket output of the modulator (use a phono plug with the centre pin cut short), or more elegantly from a Belling-Lee (TV Aerial) connector on the front panel. Special screening arrangements are desirable in the latter case, which are discussed in the Constructional Notes section of this Manual (Section 3).
The VDU-K card also provides a composite video output of a couple of volts peak to peak, for direct connection to a video monitor. This output is independent of the signal used on the card for the UHF monitor and it is therefore very easy to change over from TV to Monitor and back again, indeed to run both if required. The connection point is P3 on the card, the signal being taken from pin 1 of P3. Screened cable should be used, the screening being taken to pin 2 of P3. It is suggested that a front-panel BNC Connector be used for the Video output.
These have already been mentioned at intervals throughout the Manual so far. They are two or three in number, identified as U2, U23, and U24.
U2 is a 2516 or 5-volt 2716 type, preprogrammed with one or more programs which are used to form a timing generator. A standard preprogrammed EPROM can be obtained from the supplier of the VDU-K card, included in the kit of parts, or separately, ordered as "Timing Generator EPROM". U2 is shown on Sheet 2 of the circuit diagram, and it will be seen that its address line A9 (pin 22) is connected to S2h. As already mentioned, the usual purpose of this switch is to select an interlaced or non-interlace display format. Address line A10 (pin 19) is hard-wired to 0V, but the circuit board track can be cut so that A10 can be wired to +5V instead, and so release a second pair of timing programs, for example for a 64-character by 16-line format. 3 holes have been provided in the circuit board close to pin 19, so that a 3-pin assembly can be fitted to connect pin 19 of U2 to either 0V or +5V (never both!).
Some brief information on the way the Timing Generator Program is written is given in Section 4 of this Manual, and it likely that a listing of the program will be made available at extra cost.
U24 is a 2516 or 5-volt 2716 EPROM which contains the 128-character "Standard Character Set". This is supplied in the kit of parts or may be purchased separately as "Character Generator EPROM". In normal circumstances an EPROM is always fitted as U24.
A second group of 128 characters can be contained in a second 2516 or 5-volt 2716 EPROM. This is known as the "Applications Character Set", contained in the "Applications EPROM". These characters can be defined by the user (see Section 4 of this Manual for details), or some sets will be made available for sale for certain applications, e.g. "Chess Pieces". If used the Applications EPROM should be fitted as U23.
The types of EPROMs described so far have all been 2K in length. At the time of writing (Summer 1982) 2K EPROMs have, perhaps surprisingly, become less expensive than 1K types. It is conceivable that some time in the future a 4K EPROM may similarly become less expensive than the 2K types. To provide for that contingency, the VDU-K card has been arranged so that instead of two 2K EPROMs for U23 and U24, a single 4K EPROM can be fitted instead. This would contain 256 characters, i.e. both the Standard Character Set and the Applications Characters. If a 4K EPROM is used it should be fitted as U24, and the socket for U23 left empty.
There are two common types of 4K EPROM: the 2532, and the 2732. Unfortunately they have slightly different pin arrangements. The 2532 is close enough to the 2K types to fit in directly without any circuit changes (the VDU-K card has been carefully designed to permit this – it is by no means generally the case), but the 2732 needs some circuit changes. The alterations are all carried out on the 5-pin 0.1" pitch pin assembly P5. For all EPROMs discussed except the 2732, link pins 1 and 2, also (and separately) pins 3 and 4, on P5. For the 2732 link pins 2 and 3, and also (and separately) pins 4 and 5. Note that if some sort of plug-in arrangement is made it is a simple matter of turning this arrangement through 180º to accommodate the different EPROM, i.e. it is either the upper two pairs of pins which are linked or the lower two pairs.
Each of the displayed characters is normally an arrangementof the 80 dots which make up the 8 x 10 matrix (Further details are included in Section 4 of this Manual). The vertical parameter of this matrix, the 10 picture lines, is set by the decade counter U10, which is a 74LS290 device. This has been deliberately chosen in place of the older 74LS90 for two reasons: Firstly because it is the type now recommended for new designs, having the supply pins in the conventional positions, at the corner pins, and secondly because fortuitously it is pin-compatible with the binary counter type 74LS293.
If the 74LS293 is substituted for the 74LS290 as U10, the character matrix is extended vertically, and becomes 8 x 16. This is not normally usable, because with the normal 24 rows of characters the number of picture lines used (24 x 16 = 384, or 768 on an interlaced display) exceeds the number available on a standard TV (312 lines non-interlaced, or 625 lines interlaced).
However, for special applications, for example if the number of rows of characters (normally 24) is reduced to 16, e.g. for a 64 x 16 display, or perhaps for some graphics experiments, then an 8 x 16 character cell matrix has some attractions, since 16 rows of characters each of 16 picture lines occupies 256 lines in total (512 interlaced), which conveniently fills the screen almost from to bottom.
Some people certainly favour a tall thin matrix for alphanumeric characters, considering that they look less like those used in childrens’ books (i.e. short fat characters).
If experiments along these lines are to be conducted, then some attention will be necessary to the Timing Generator EPROM to reduce the top and bottom margins, and increase the picture area.
This concludes the discussion on the various options open to the user of the VDU-K card.
The circuit diagrams in Section 5 of this Manual will be taken as the basis for the detailed circuit description. The Manual is already in danger of becoming inconveniently long, and so it will have to be assumed that a certain amount of background knowledge is possessed by the user.
Mostly, the components on the diagrams and in the parts list use the designation letters specified in ANSI standard Y32.2-1970. In a way these letters are fairly irrational (e.g. "J" is a connector, "Q" is a transistor, "U" an integrated circuit, and so on), however as it is a standard it has been adopted here. The component overlay diagram uses the same designations as for the circuit diagrams.
A block diagram is provided, which also serves as a "map" showing the user where he may find the particular section of the circuit in which he has an interest. Each of the sections represent a logical unit of the whole circuit. Particular care has been taken when preparing the diagrams to ensure, as far as is reasonably possible, that the diagrams begin at the top-left hand corner of the drawing, and continue downwards from left to right. Another convention which has been followed as rigorously as possible is to have the inputs to the left of each circuit block and the outputs to the right. Although this is a very logical and sensible approach to drawing circuit diagrams, it is surprising how often these ideas are disregarded.
In order to include the information which it is desired to present on the circuit diagrams (pin numbers, function names, power supply pins etc.), it has been necessary to use several sheets of paper. However great care has been taken in partitioning the diagram to turn this apparent disadvantage into a positive advantage, by breaking the circuit up into individual sub-functions which are more easy to understand a step at a time. Even the order of the various sheets has been given close attention, so that as far as possible the source of a signal is shown on an earlier diagram before it used on a later one. All signals which connect to a part of the circuit on a different page are given names, and their source or destination is shown in the form (e.g.) SIG1 3/10,12(4);6/9(5). This example means the signal called SIG1 is connected to U3 pins 10,12 on the circuit diagram sheet (4), and also U6 pin 9 on sheet 5 of the diagram.
So as not to interfere with the logic flow, not all power supplies are shown on the integrated circuits drawn. Instead, each sheet of the diagram contains a table of the integrated circuits on that sheet, their type number, and their power supply connection pins. This does not apply to power supply connections which represent a logic level input, for example 0V for a logic "0", or +5V for a logic "1"; these are shown connected to the integrated circuit pins. An effort has been made to show all pins of each integrated circuit, even the ones which are not connected to anything else. Such pins are marked "NC", which means "not connected".
The Parts List is to be found at the very back of the Manual, for easy reference. It is organised in two ways; firstly by component reference number, which gives the component value if the reference number is known, and secondly by component value, which gives the reference numbers of all the components which have that value. The latter method is more convenient when checking a kit of parts and assembling the card, for example it is often useful to know where all of the components of a given value should be located if you finish construction and find one or two items left over. Later, you will want to know the value of a component of a given reference number, and the first method of forming the parts list will be more appropriate. To minimise the well known chore of searching all over a circuit board seeing if you can find say C11, or R17, which have become temporarily invisible, the components on the component overlay have been numbered in ascending numerical order starting at the top left-hand corner and working across and down to the bottom right. (So if you are looking for an elusive R17, you will know you are getting warm if you see R16 or R18 – R17 won’t be far away.)
To help users carrying out tests on the card, or wishing to modify it, both ends of such components as resistors and non-polarised capacitors are identified on the circuit diagram, for example if it is wished to check the reset pin of Ul (on sheet 2 of the circuit diagram) it can be seen that it is connected to end 2 of R9, end 1 of R9 being connected to +5V. On the component overlay diagram horizontally positioned components should be taken as having end 1 to the left and end 2 to the right, whereas vertically positioned components should be taken as having end one to the top of the diagram, and end 2 to the bottom. In an effort to help users all components have been placed on the card in a similar direction, so that for example all the ICs are the same way round, similarly the electrolytic capacitors and diodes.
Section 5 also includes various timing diagrams, which may be an aid to understanding certain parts of the circuit.
As the circuit diagram has been drawn split up into logical blocks, these represent convenient sections into which the circuit description may be divided.
This shows the complete circuit in block form. In Sections 2.1 and 2.2 of this manual general descriptions of the way the card works have been given and it is now time be more specific. The block diagram is a little like having the whole circuit diagram on one page, and is of course fairly comprehensive as a result. Once it has been studied it should be thought of as a "map" showing where to find the detailed diagram corresponding to each block, and to this end the appropriate sheet number of the circuit diagram is given beneath each block.
The essential function of the VDU-K card is to provide what can be termed a "window" into the memory of the computer system. It has a "1K Video RAM" (shown on the block diagram slightly below right of centre) which can be written to and read from, similarly to any of the other RAM in the system. The significant difference is that the data in this RAM are also being continually processed on the VDU-K board in such a way as to render them visible when viewed on a TV or video monitor screen. A fair amount of circuitry is necessary because of the demands of the TV system, which requires 50 complete screenfuls of information per second, correctly organised into a composite video waveform having the appropriate pattern of dots correctly synchronised with the required frame and line synchronising pulses. In very cheap systems some of the burden of this activity is borne by the system microprocessor, with an inevitable reduction in performance of one kind or another, but on the VDU-K it is all carried out on the card, and the main system microprocessor is not slowed down or restricted in performance in any way.
The block immediately preceding the 1K Video RAM is entitled "Multiplexer". This is the technical term for the circuit which switches the address lines over to the System "Address Bus" when the microprocessor is programmed to read from or write to the Video RAM. The appropriate signal is given to the multiplexer by the output of the "Address Comparator and Control Logic" block, which is set up (by selection links or switches, and various gates) to give the signal when a read or write of the Video RAM is required. At the same instant the "Monostable" is fired, which immediately freezes the "Octal Transparent Latch" to ensure that the data which were previously coming from the Video RAM, and which are destined to be viewed on the screen, are held safe while the microprocessor read or write is carried out. It is is this latch which is central to the method used on the VDU-K card to produce "no snow".
The "Octal Data Bus Transceiver" is "enabled" at this time and connects the data bus to the data lines of the Video RAM and the read or write is carried out. (The tranceiver has a direction control, not shown on the block diagram, which sets its read/write direction appropriately). Although these data are also presented to the inputs of the "Octal Transparent Latch" its outputs are unaffected as they are held latched by the signal from the monostable.
After the microprocessor read or write is over, the multiplexer reconnects the Video RAM to the on-board addresses which are looking after the supply of correct information to the screen. Fast RAMs are used and soon the data outputs from the RAM are correct for feeding on to the screen. The monostable is arranged to "time out" just after the data are correct, and so render the octal transparent latch transparent again. The timing of the circuit has been worked out most carefully to ensure that with a Z80A-CPU microprocessor operating at 4.0 MHz, there is never any disturbance of the displayed picture even if the microprocessor is continually accessing the Video RAM. The various timing diagrams in Section 5 includes one which shows how the method works, and one which illustrates the timing for the "block move" instruction of the Z80A-CPU. This is the most stringent of all for the VDU-K, since it involves the Z80A-CPU issuing a consecutive read and write without the normal breathing space when the op-code is fetched or re-fetched.
The above part of the Block Diagram has been covered first, perhaps out of its logical order, so that all of the above points can be assumed known in what follows.
The top left-hand corner of the Block Diagram will be taken as the starting point for the remainder of the Block Diagram description.
This shows the "12 MHz Oscillator", which is crystal controlled by a 12 MHz quartz crystal. In fact 6.0 MHz is the maximum frequency required on the VDU-K card, but twice this frequency has bean chosen to make life easier for any users who are carrying out experiments to double the clock rate, for example to obtain a 64-character format.
The 12 MHz is divided by 2 to give a 6 MRz signal which is used as a "Dot Clock", and further divided to provide various other signals, and a 3 MHz signal is obtained to be the input to the "Active Pull Up". The active pull up transforms the logic "1" level from the normal TTL value of 2.5-3.5 volts to near enough a full 5 volts (it also inverts the signal in the process but this is immaterial). It is a great shame that the miracle of integration which puts 40,000 transistors on a chip in the Z80A-CPU does not extend to providing as well the extra transistor Q1 which is used for the active pull up.
The output of the active pull up is used as the clock input to the "Z80A-based TV Sync. Generator". This is, as far as is known, a unique design which is an excellent example of how a two-chip microprocessor system (the Z80A-CPU and the 2716 EPROM) can give cost and space savings and yet provide performance advantages over more conventional designs. There is no need for any RAM here as there is sufficient contained within the registers of the Z80A-CPU itself. If anyone is sufficiently impressed to copy the idea themselves, they are welcome to do so; we will be less likely to get cross however if they make if clear where they first saw it!
The choice of 3 MHz is no casual choice; one of the time intervals in the CCIR television standards, which is the basis of those we use in this country, is 2.33 microseconds. This is 7 Z80A "T" states at a clock frequency of 3 MHz, which is very convenient because 7 "T" states is the time it takes to execute many of the instructions in the Z80A set. At this clock frequency one picture line (64 microseconds) is exactly 192 "T" states. There is a little more on this subject in Section 4 3 of this Manual.
Referring again to the "Dot Clock", it should be noted that although this is 6 MHz, it does not mean that the dots on the screen are issued at this frequency. The maximum equivalent frequency of the dots is when they are alternately black, white, black, white, and so on. Since they come from a shift register which is being "clocked" at a 6 MHz rate, i.e. six times per microsecond, they will be dots of one sixth-microsecond duration. The frequency of a signal which is say black for one sixth of a microsecond then white for one sixth of a microsecond before it goes back to black again, is in fact only 3.0 MHz, since the period of the waveform is one sixth plus one sixth, making one third of a microsecond, i.e. frequency 3 MHz. As the waveform to produce the dots is a squarewave it requires a much greater bandwidth than 3.0 MHz for accurate reproduction. The TV set video bandwidth is about 6.0 MHz, which proves sufficiently wide to give a first-class picture, and so avoid the expense of a video monitor unless one is already available.
The next block to be mentioned is the "32-Character Counter". This counts a signal which has a duration equal to each one of the displayed character cells, and the outputs are presented via the multiplexer to the address lines of the Video RAM. In this way 32 sequential locations in the RAM are selected in turn, and provide data which are ultimately directed to the display.
The next block is the "10-Picture Line Counter" which advances by one each time a count of 32-Characters is completed. This continues until all 10 picture lines have been counted. As each picture line is counted the same set of data is provided by the Video RAM. The same data are used because the characters are 10 picture lines tall, and 10 identical passes through the video RAM are necessary to build up each complete row of 32 characters. Although the characters remain 'the same for each 10 picture lines the dots making up those characters do not, and so the 4-bit outputs from the 10-Picture Line Counter are connected to the Character Generators. More will be said on this subject when the character generators are discussed.
After 10 picture lines have been counted it is time to proceed on to a.nother row of characters on the screen, so after 10 counts of the picture line counter the "24-row counter" is advanced by one. The outputs of the row counter are used as further addresses in the video RAM, and a whole new set of data is issued for each count of the 32-character counter. As before, this new set of data is repeated for 10 consecutive picture lines, at which point the row counter is advanced by yet another count and another new row of data is addressed in the video RAM.
After the final picture line of the 24th Row is complete, all of the counters are reset by signals from the Z80A-based TV Sync. Generator, ready to begin again for the next T.V. picture "frame". It is implicit in the method that the whole sequence repeats regularly fifty times a second, to provide the illusion of a permanent display on the T.V. or monitor screen. The display is of course made up in the same way as any T.V. picture, i.e. by controlling the output from an electron beam as it is rapidly scanned down the screen, li.ne by line. It is essential that the motion of the beam is precisely synchronised with the output from the VDU-K so that each time the picture is retraced it is in exactly the correct position. For a non-interlaced display successive "frames" should be in precisely the same position, and for an interlaced display successive frames are moved alternately up or down by half the distance between lines to give the illusion that there are twice as many lines on the. display.
The standard T.V. Sync Generator produces all the necessary sync. pulses for interlaced and non-interlaced displays, to force the television or monitor to begin its electron beam scan at just the right moment.
The final few blocks on the Block Diagram are at the foot of the page. The first is the "EPROM Character Generator(s)". The "Select Switch" chooses whether a single 128-characters plus their reversed set are used or a full 2 x 128-characters are to be used, by adding the "Applications EPROM". The EPROM used has inputs to its address lines and is programmed with carefully chosen corresponding data at its output lines. The higher order address lines come from the data outputs of the video RAM, and the lower order address lines come from the 10-picture line counter.
As the 32-character counter cycles rapidly through the addresses of a row of characters, the corresponding data in the video RAM are presented to the character generator EPROM as addresses. The characters can be the same or different, but whatever they are they each provide access to a unique block of addresses within the EPROM. The individual addresses within the block are provided by the picture line counter, so that as it counts it can access the data needed for successive lines.
The pattern of dots which has been programmed in the EPROM to correspond to the particular character code, and just as importantly to correspond to the precise line of dots within the character cell, is output on the eight data lines of the EPROM, and loaded in parallel into an eight-bit shift register just before the character counter proceeds to the next character address. The shift register is "clocked" continuously at a 6 MHz rate and while it is providing the eight dots for the current character there is time for the next group of eight dots to be obtained from the EPROM.
The block marked "Synchronisation" includes the circuit which brings together the video signal (the pattern of dots) and the T.V. sync. pulses, converting them to two "composite video" signals. One of these is suitable for driving the final block the "UHF T.V. Modulator" which provides a signal suitable for direct connection to a T.V. aerial socket, and the other is slightly different in level and is suitable to connect to a T.V. monitor which accepts a composite video signal of a couple of volts peak to peak.
Another function performed by the earlier block "Synchronisation" is to ensure that the signals which gate the dots are exactly timed, so that for example the reverse video signal and the signal which defines the left and right hand margins coincide exactly with the start and finish of the individual dots. If this is not done the display can show unwanted "ghost" dots in certain positions, and exhibit annoying discontinuities where characters adjoin.
This concludes the Block Diagram Description. We are now in a position to proceed to the detailed description of the individual sheets of the circuit diagram.
Starting at the top left hand corner of this diagram two inverters type 74S04 form a cross-coupled multivibrator having a crystal in place of one of the capacitors. This constrains the circuit to oscillate at the crystal frequency. A 74S04 is used rather than the more common 74LS04 because experience with this particular oscillator circuit has from time to time in the past not been entirely satisfactory when certain combinations of crystal and 74LS04 have been used. A further 74S04 inverter acts as a buffer for the 12 MHz signal, so that an oscilloscope probe can be used during test without disturbing the operating conditions of the oscillator. U14 is a 74LS393, a dual binary ripple counter which divides the 12 MHz by successive powers of two. Note that the first section has its reset line permanently earthed so it is simply a divider, whereas the second stage has its reset pin 12 connected to the reset signal R, and so it is acting more like a counter, starting from a fixed point, all zeros. Some of the signals so far discussed are included on one of the timing diagrams, but they will be mentioned again in the description of the diagram on sheet 6.
A 74S04 drives the Z80A-CPU clock input from a signal called "3 MHz", and Q1 is a general purpose PNP transistor which is used as an active pull-up to ensure that the clock signal rises sharply to nearly +5V when required (this being a special requirement of the Z80A-CPU clock circuit which unfortunately is not guaranteed to accept a normal TTL level clock). R8 limits the base current to Q1, C8 provides increased transient drive to turn Q1 on more quickly, and also removes excess charge from the base to turn Q1 off quickly a short while later. R7 assists in this latter endeavour. C8 is sometimes called a "speed up capacitor" because of its purpose. R3 limits the current which passes through Q1 on those inevitable occasions when for a brief instant U8 pin 8 is conducting to ground and Q1 is conducting to +5V. Rumour has it that R3 also plays a small part in tailoring the rise and fall time of the waveform to suit the Z80A-CPU specifications.
U1 and U2 represent a small microprocessor system dedicated to the task of producing all of the specialised timing pulses, most notably the complicated T.V. Sync waveforms for interlaced and non-interlaced displays. A timing diagram for the various pulses produced is included in Section 5.2 of this Manual. Some of the inputs to the Z80A-CPU (pins 16, 17, 24, 25) are strapped high via resistor R6. These are inputs which are not used in this simple sub system. The reset line U1 pin 26 is held high by R9. At power on C11, which is also connected to pin 26, is discharged and holds the Z80A-CPU reset so that it starts executing its control program, held in U2, from a known point, once correct operating conditions (power supply, clock, etc.) are established. Once C11 has charged sufficiently (via R9) the reset condition is released, and U1 begins its normal operation. The purpose of CR1 is to discharge C11 quickly when power is removed, so that it will be ready to provide a power on reset again if power is restored quickly, also CR1 provides a direct discharge path for C11 when power is removed to prevent C11 discharging into pin 26 of U1. In the interests of economy no limiting resistor has been provided in series with C11, so a diode with a good surge rating has been specified for CR1.
Only two control strobes from the Z80A-CPU are used, Read (pin 21), and Write (pin 22). Such signals as !MREQ, !IOREQ, !BUSAK, !M1, !RFSH, are entirely superfluous in this application and no connection is made to these outputs. There may be more than one control program held in U2 (selected by altering the levels on U2 pin 22, and U2 pin 19, one via S2 pins 8,9 and the other via a cuttable circuit board track), but none of them exceeds 0.5K in length, therefore the nine Timer Address lines TA0 to TA8 are sufficient, indeed in this case the partial addressing is beneficial because the program is always constrained to run in the single 0.5K space, and is less likely to get "lost" (through e.g. supply line transients, inadvertant short circuits with test probes and the like). Whenever a read is carried out, i.e. an op-code fetch, the Read line goes low and enables U2, the only memory device in this small system. The data flow," along the Timer Data bus TD0 to TD7.
At the appropriate instant, accurate to the exact "T" state, suitable data will be written to the hex D-type flip-flop U13, type 74LS174. As only four signals are required, there are two lines spare for some alternative needs which may arise. According to the precise data written to U13, and their precise timing, all of the signals needed on this card can be synthesised, saving a money and board space, and as a bonus permitting much improved flexibility. The four signals are called V, H, R, and S. They are drawn on the timing diagram in Section 5 of the Manual, but it is appropriate to mention their purpose now.
"V" is a signal which resets the vertical counters (picture line, and character row). The signal is high during the top and bottom blank margins on the screen, resetting the counters (see Sheet 4), and goes low in the active picture area letting the counters count out the number of lines, and character rows.
"H" is the horizontal picture enable signal. It is low during the top and bottom blank margins, blanking the picture throughout these lines, and during the active picture area it goes high for a 42.66 microsecond interval during each line, 42.66 microseconds being the exact time necessary to display 32 whole characters at the chosen dot clock frequency, the space on each side defines the left and right hand picture margins.
"R" is the reset signal. It is immaterial what level it is during the top and bottom margins, since nothing is being displayed at this time (but the present version of the Timing EPROM sets it high in the top and bottom margins). Its main purpose is to reset the 32-character counter immediately before the active part of the H signal on each displayed picture line. These counters are not left running as they have to begin at zero at the start of each displayed line in order to count out the 32 characters in the same order for each and every displayed line. The size of the reset pulse is not critical, and it happens to be convenient to make it 8.66 microseconds, in at least one version of the Timing Generator EPROM.
"S" is the much discussed T.V. sync. signal. A glance at the waveform diagram will show it is particularly complex at the start and finish of each frame, but during the top and bottom margins and the central picture display area it is a simple regular pulse. The CCIR standards require it to be a 4.66 microsecond pulse repeated every 64 microseconds, i.e. at the start of each and every picture line.
Two of the inverters in U8 are uncommitted, and they are shown at the foot of Sheet 2 of the Circuit Diagram.
The upper six bus address lines, AB10 to AB15, are compared with the six address selection switches (or links). The switches must be set to the complement of the desired address. This is fairly easy to remember since this result in the switch to be ON for a ONE in the chosen address, and OFF for a ZERO. The detailed switch settings have been discussed in Section 2.3 of this Manual. When the address on the bus matches that set on the switches as described, the outputs of all the open collector EX-OR gates (U7 and U12, type 74LS136) which are wired together go high. It is a unique selection since a mismatch on any of the lines would cause the output of that EX-OR gate to go low, so pulling down all the others. It should be noted that the action described so far is all conditional on U12 pin 4 being low at this time. It will be low provided both inputs to U5 (pins 9 and 10) the OR gate which precedes it, are also low. In turn this means that the refresh line has to be high, and memory request has to be low. These latter conditions prevent the VDU-K card responding if it happens to be set to an address which is present on AB10-15 during either Refresh or an I/O transaction. (For Z80A-CPU use S2 pins 7 and 10 will be open, enabling U6 pin 9.)
For other processors, which do not provide or simulate the Z80A-CPU NRFSH line, a position is provided for a resistor R21 which will hold this line high if required. Also some other processors may issue their address so early in their read or write cycle that the microprocessor access to the VDU memory may be prolonged unduly, so causing "snow" on the screen. An example of such a processor is the INS-8060, or SC/MP. If this is in use S2 pins 7 and 10 should be closed. This will prevent the address match being found until either a read or write strobe is actually present, much later in the cycle. (This is achieved via the action of the output of U5 pin 3, which only goes high when a NWDS or NRDS strobe is present. Before this its output is low, which forces U6 pin 8 high, hence U5 pins 9 and 8 and thus makes U12 pin 6 low, preventing a match of any addresses.)
Once a match is found the signal SELMPU goes high, !LATCH goes low and the monostable U3 is fired which will prolong the !LATCH signal even when SELMPU is over. SELMPU also enables U6 pin 2 so that its output pin 3 can follow the state of the NWDS bus line (in the absence of SELMPU its output is permanently "Read"). Similarly it enables U6 input pin 13 so that the output pin 11, a signal called !BUFFEN will go low, enabling the buffer in the presence of either of the strobes NWDS or NRDS (in the absence of SELMPU, !BUFFEN is always high, i.e. the buffer is not enabled).
A signal DIR, which is the direction control for the data bus buffer on sheet 5 of the diagram, is derived from the NRDS line, on the basis that when the micropocessor is not reading it must be writing.
The duration of the monostable is made adjustable, so that it can be "fine-tuned" to suit the particular delays etc. present in the components on the card. It is very easy to adjust without special equipment since it simply needs adjusting for the minimum "snow" on the display. Maladjustment causes no problems other than an inferior picture so it is not at all critical.
These are fairly straightforward as their purpose has been extensively discussed in the Block Diagram description, and the source of the R and V signals has been discussed in the description of the circuit on Sheet 1 of the diagram. The 32-character counter outputs are C0-C4, the 10-picture line outputs are PL0-PL3, and the 24-row outputs are R0-R4.
However the layout of the signals C0-C5, and R0-R4 on the diagram needs some comment. This arrangement has been provided for the convenience of users who are wishing to experiment with 64-character lines. In order to count double the number of characters in the same time interval the input clock "0.75 MHz" must be doubled and an extra character counter line (C5) provided. If C5 is connected to the video RAM it will displace the first row-counter line R0, which in turn must be moved down to R1, which will have to move to R2, and so on, eventually R4 having no place to go; a result of the fact that only 16 lines of 64 characters will use up the whole 1K video RAM (64 x 16 =1K). If the original 24 lines are required, extra RAM must be added, to accommodate the displaced R4 row counter.
The circuit diagram reflects the actual track layout on the card, (for the symbolism see Sheet 8 of the circuit diagram), so as to ease the task of those users who are straying from the straight and narrow in wanting to alter the format of the VDU-K. By the way it is suggested that such users contact the user group "Interaktion" who will almost certainly be publishing hints and tips on this subject in their newsletter.
The multiplexer comprises U16, 17, and 18, the control input in each case being the SELMPU signal. SELMPU is high when the microprocessor is executing a read or write of the video RAM (U26 and 27), and it causes the various "A" inputs of the Multiplexer to be switched over to the "3" inputs, which in the main connects the address bus AB0 to AB9 to the video RAM rather than the Character and Row counters C0-C3 and R0-R4. Thus SELMPU gives control of the video RAM over to the microprocessor, ready for a read or write. An extra line which comes out of the multiplexer is !CS which has to be low to enable the RAM. Normally !CS is connected to 0V via U18 pin 11, but this signal is obtained from U18 pin 10 i.e. !BUFFEN when SELMPU is high. This is all shown on the timing diagram in Section 5, where it will be seen that in the case of a read !BUFFEN is also 0V, so the video RAM remains selected, but in the case of a write !BUFFEN is high for a little while before it goes low for the write. This short time is quite significant because it causes the outputs of the video RAM to go tri-state in anticipation of having data thrust upon them when the data bus buffer U19 is enabled in the direction for a write.
Had !CS been wired to a signal which was permanently low no particular change in operation would be observed, but there would be a bus "contention" when the buffer forced data onto the data lines of the RAM before they had time to go tristate for a write. The contention would only last for sixty nanoseconds or so, but while it did the +5V rail effectively would be short circuited to 0V, via the output drivers of the RAMs and buffers on each line which was in conflict. The 74LS645 is a very powerful driver so it would probably win over the RAMs, so it is likely that the RAMs would bear the brunt of the short circuits described. The 2114L RAM is however very robust and it is unlikely that failure would result. A more subtle problem could be the production of a large amount of system "noise" (spikes etc.) which could conceivably corrupt some data somewhere, trigger some latches and so on.
A lot of fuss is being made over this point because it has to be considered if extensive modifications are made to the VDU-K card which result in alteration of the !CS arrangements.
The signals on pin 15 of the multiplexer ICs are wired low so as to enable the outputs permanently.
Note that U17 pins 5, 6, and 7 are spare, and can be used for any experimental purpose.
U19 has already been mentioned. It is enabled by the !BUFFEN signal which goes low when SELMPU is high and there is either a read or write strobe present. The direction is controlled by a signal called DIR which is derived from the Read strobe from the Bus, on the basis that when the microprocessor access is a read it is a read, and when it is not a read then it must be a write.
The final IC on this sheet of the diagram is U25, the octal transparent latch. Normally its control pin 11 is high which renders it transparent i.e. the data on the inputs D flow through to the outputs Q, but the instant a microprocessor access begins the latch is rendered "opaque" or "frozen" by the low on pin 11. This action preserves the current data for the circuits which follow it, since these data would otherwise almost certainly be corrupted by the microprocessor access, causing "snow" on the screen. Since the LATCH signal is extended by the action of the monostable which produces it, the latch only becomes transparent again after the data from the video RAM have returned to valid values for the current character for display.
The internal labelling of U26, U27, and U25 deliberately does not distinguish the various inputs and outputs, so that for example the address lines shown within U26 are all marked "A", and the outputs are all marked "0". The reason for this is that they are all interchangeable, i.e. it doesn't matter at all at what physical location within the chip the data are stored, just so long as reading that same address will result in the same data being output (which of course they will on the basis of what goes in comes out). Similarly, the eight "D" inputs in U25 are in no particular order, as they represent eight interchangeable inputs, (but note that the "Q" outputs have to correspond directly to the appropriate "D" inputs, so that for example output pin 12 is the Q output of the D input which is connected to the D input opposite it on this drawing, namely pin 13).
This part of the circuit is the part which turns the data in the video RAM (generally held as an ASCII code) into the pattern of dots which will form the visual representation of that character on the screen.
As each character in the video RAM is held in the form of a single byte, and each character on the screen comprises a matrix of eighty dots (8 x 10), the central part of this circuit provides the means for a single byte input code to release the corresponding pattern of eighty dots.
Ignore for the moment LD7, and the circuit which is adjacent, and imagine that a (7-bit) ASCII code from the video RAM has been latched on the seven ("latched data") lines LD0 to LD6. Furthermore, increase the power of your imagination to assume that only U24, the "standard" character generator EPROM, is present, and U23, the "applications" EPROM, is not.
Suppose that the character to be displayed is some letter, say letter "A", which is represented by the ASCII code 41 (hexadecimal). This code is therefore present on the seven lines LD0-LD6 which contribute the high order lines (A4 to A10) of an address in the EPROM. The lower order address lines (A0 to A3) are contributed by the four lines from the "picture line counter", PL0 to PL3. The picture line counter, it will be remembered, starts at zero, and is advanced by one count at the end of each displayed picture line, until 10 complete lines have been displayed, at which point it goes back to zero again. The successive counts of the picture line counter access ten successive locations within the EPROM, and eight bits of data are output on lines D0 to D7 for each of the ten counts. This is all for the same single character to be displayed ("A" in our example), which explains how the single ASCII character from the video RAM is transformed into a pattern of 80 dots (8 x 10) on the screen.
In each of ten passes, eight dots are obtained from the character generator, which of course has been programmed with the appropriate pattern to produce the character in question. All 0's would be black, and all 1's would be white, but usually there will be a mixture of 0 s and 1's, spaced out suitably to form a recognisable character.
The reason for using the dots eight at a time is mainly because common EPROMs have eight bits stored in each location, but it is very convenient to deal with eight at a time, since this means the accesses to the video RAM, EPROMs and so on can be relatively leisurely, which means in turn that readily available components can be used (i.e. not expensive high speed types).
As the pattern on the screen is displayed a single dot at a time, the eight dots from the character generator are loaded in parallel into a shift register (U22, type 74LS166), which has a single serial output. A synchronous shift register is used, the term synchronous meaning that all of the actions in the shift register are governed exactly by the signal on its clock input pin 7, (in this case the 6.0 MHz "dot clock"). This is important because for certain characters on the screen (e.g. a fine "chequerboard" pattern of alternating black and white dots) any slight deviation from perfectly even timing, say when a new character was being loaded, would result in visible "joins" between what should be an unbroken display on the screen.
The S/!L input U22 pin 15 is high for shifting, and low to load in a new character on the eight input lines connected to CD0-CD7. Pin 15 is made to go low, to load a new character, just after the last dot of the previous character is passing through the shift register. In a normal asynchronous shift register, loading would occur at once thus spoiling the timing of the previous dot, but in this type the action is delayed until the next clock edge, so that the timing of the last dot of a character is identical to that of those dots which went before. Of course when the register is being loaded it is not being shifted, so it might be thought that one dot might be lost, but in fact the first dot of the next character does not need shifting into position; when the register is being loaded the data from input line CD7 into DH (pin 14) automatically flow through to output Qh (pin 13) to become the first dot of the next character, without the need to be shifted until the next clock pulse, by which time the S/!L input pin 15 has returned high.
The two 3-i/p AND gates and the U4 pins 1, 2 inverter shown in the top right hand corner of the diagram decode the binary count signals "6.0 MHz, 3.0 MHz, 1.5 MHz, 0.75 MHz", so that the S/!L signal is given at the correct moment during the timing of each character. The Timing Diagram given in Section 5 of the Manual shows how these signals are produced, including the one named "next character", which is discussed below. If you do refer to the timing Diagram, bear in mind that it is idealised - as the counters used are ripple counters (for reduced chip count and low cost), the various outputs do not all change simultaneously. At the 6 MHz dot clock frequency the propagation delays are not so big as to cause any difficulties, but for experimental use at a 12 MHz dot clock frequency the delays are great enough to cause a delay of around half a 12 MHz clock cycle – effectively inverting it on the Timing diagram. For this reason an inverter has to be put in the clock line when experimenting with the 12 MHz clock frequency.
The two 3-i/p AND gates and the U4 pins 1, 2 inverter also produce the signal shown as "next character", which marks the exact end of each character. This signal will be shown on the next sheet of the diagram (sheet 7), where it is used to ensure that signals which affect the characters, e.g. reverse video signals, and the "H" signal which defines the margins, are as exactly synchronised as possible with the characters. This prevents for example small "pieces" of characters from straying into the edge of the margins, which would spoil the presentation of the display. In older designs this effect was not a problem since the alphanumeric characters were located in the centre of a blank box, and it did not matter if the blank box strayed into the margin – it was invisible anyway. However, the VDU-K permits each character cell to be black or white including the whole cell, entirely at the user's option, hence the need for attention to this point.
It will be difficult for the less experienced user to understand the point of all the discussion above, regarding the various possible imperfections, as he will imagine that all VDU designs are executed implicitly to the same standards as the VDU-K, which older users will know is by no means universally the case!
Assuming that the reader has some sort of grasp of the circuit so far discussed, we can move on to the signal LD7 which was disregarded before, and also the "applications" character generator U23.
As the video RAM stores eight bit data (latched as LD0-LD7), and the ASCII code is only 7-bits (LD0-LD6), the remaining signal LD7 is "spare". In this design it can be used for either of two purposes, selected by the user, permanently, or switchable.
The first purpose is simply to provide a complete repeat of all 128 characters so far available, but this time in "reverse video", so for example writing the ASCII code C1 (hex ) in the video RAM will result in a reverse video letter "A" being displayed, since C1 (hex.) is derived from 41 (hex.), the code for the normal letter "A", by setting its highest bit to 1.
The second purpose is to provide a totally new set of 128 characters, in addition to the first 128, making 256 in all. Depending on the application the second set of characters may include some letters (e.g. a reverse video letter "A" for code C1 hex. to give the same effect as before) and some new graphics characters, or of course the new characters can be entirely different, whatever the user wishes.
In summary, the eighth bit can be used for selecting one of two alternatives; the same characters as before, but in reverse video, or a totally new character set. It is desirable to be able to select these by a switch, according to the needs of the actual program being run at the time, and the VDU-K offers two alternatives for the implementation of this switch. The drawings at the top left of the diagram symbolise the physical arrangement on the board. The 8-pin DIL area can be fitted with a DPDT DIL (double-pole double-throw, dual-in line) switch, or fixed wire links. This is not the preferred arrangement because such a switch is very rare, and also the board has to be removed from the system to make the change. (The DPDT DIL switch mentioned is very difficult to obtain, and the more common type 2 x SPDT can be used instead, but this has the drawback that as the switches cannot be operated simultaneously it is mandatory to remove the power before changing the setting.)
The preferred arrangement is to use the two rows of pins, Pl and P2, to provide a connection area for a conventional DPDT switch mounted on the front panel, and fit nothing in the DIL socket. (This preference is of course only for general use of the board, with a front panel. If no front panel is fitted, and/or the switch is not required then the other arrangements will be found most useful.)
Whatever arrangement is made the circuit function is fairly straightforward. A single line LD7 is an input to this part of the circuit, and there are two outputs; one to the first EPROM U24 via a link and the second EPROM U23 via inverter U4/3,4; another is a signal called REV (which stands for reverse video). LD7 is routed to one or other of these outputs and the other output, whichever it is, is earthed. In the REV position of the switch (marked on the diagram), LD7 is connected to REV, so that reverse video is under the control of LD7, and U23 (if fitted) is turned off, since its chip enable line pin 18 is driven high by the low on the input of the U4/3,4 inverter.
In the alternative switch position U23 pin 18 receives an inverted version of the LD7 signal, and is thus enabled whenever LD7 is high. REV this time is always low and no reverse video is applied (except of course for any reverse video characters which may be programmed into U23).
It has been assumed so far that the "EPROM type selection links" shown on the diagram are in the solid positions, and that 2K EPROMs type 2516 or 2716 are in use. In this case it can be seen that the two EPROM chip enable input pins 18 come from the same source, but inverted in the case of U23. Thus when U24 is "on", U23 is "off", and vice versa. This technique is in effect turning the two 2K EPROMS into a single 4K block, and nowadays single 4K EPROMs are readily available, so some users may prefer to use one of these instead. The various EPROMs available have similar pinouts, to a greater or lesser extent, according to their type and size.
One common 4K EPROM, the type 2532, is so similar in pinouts to the 2K types, that it can in this design (not always in other designs!) be fitted in place of the 2K type, with no circuit changes. If this is done, the 2532 device should be fitted in position U24, and U23 left vacant; The 2532 should be programmed with both sets of characters, the "standard" character set in the first 2K, the "applications" set in the second 2K.
The reasons no circuit changes are required for this substitution is that pin 18 on the 2532 conveniently is the extra address line (All) which 4K EPROMs have, and the other pins (20, 21) can still be connected to 0V and +5V respectively although their function has changed.
Another common 4K EPROM is the type 2732. In principle this can be used to replace the two 2K types in the same way as discussed above, but sadly it is not quite so pin-compatible as all the others. When a 2732 is used it should be fitted in position U24, and U23 left vacant. It should be programmed as indicated for the 2532 described above. However, most importantly, the EPROM selection links should be altered from the solid positions to those shown dotted. The arrangement of links on pin area P5 has been carefully chosen so that the two settings required are symmetrical; in one case the top two pairs of pins are connected, and in the other it is the bottom two. If some form of reversible connector is used to make the connection it can be arranged to convert the board from one type of EPROM to another simply by reversing the connector, or if a 2 by 2-pin jumper link arrangement is used it can be moved up or down by one position to make the change.
The reason for these changes being necessary in the case of the 2732 is that the A11 address line is on pin 21, not pin 18 as before, and pin 18 has to be connected to 0V. As in the case of the other types of EPROM the function of pin 20 also is changed, but it should still be connected to 0V as before.
The description of this part of the circuit can begin in the top left hand corner of the diagram. U20 is a positive edge triggered dual type "D" flip-flop, the clock inputs in each case being triggered by the "next char." signal which was developed in the circuit shown on sheet 6 of the diagram. There are two signals which control the display of characters on the screen; "H" which defines the horizontal margins ("H" is low in the margins, high to display), and "REV" which is high if the current character is to be displayed in reverse video, for a "clean" display it is vital that these signals be synchronised exactly with the "next char." signal which defines the exact point of transition between one character and the next. The "Q" outputs U20/5,9 take up the levels of the "D" inputs (U20/2,12) in exact synchronism with the clock ("next char."). The purpose of C18 will be mentioned in a moment.
The U20/5 output (derived from the "H" signal input) enters AND gate U15/10,11 and so the U15 output pin 8 is unconditionally low when "H" is low (i.e. in the margins), and follows the U15 input pin 9 in the display area (where "8” is high). U15/9 comes from U12/8. (R10 is merely a pull-up resistor as U12 is an open collector device.) U12 is an EX-OR gate which has two inputs, pins 9 and 10. Pin 10 is a signal called "dots" which is the serial pattern of dots from the shift register, and pin 9 is derived from the "REV" signal, which is high if the current character is to be displayed in reverse video. The feature of the EX-OR gate which is used here is the fact that its output pin 8 will follow its input pin 10 when pin 9 is low (i.e. normal video), but its output will give an exactly inverted version of input pin 10 when pin 9 is high (i.e. reverse video).
The pattern of dots, inverted or not inverted as the case may be, passes through U15/9,8 under the margin control signal U15/10,11 already described. When the circuit was designed the reverse video feature was to be achieved by programming reverse video characters into the second EPROM, and it was only an afterthought to provide for this also in hardware by adding the U12/9,10,8 EX-OR gate. An unfortunate consequence of adding this additional feature is that the signal path from U20/9 to U15/9 is delayed by the EX-OR gate, when compared with the signal path from U20/5 to U15/10,11. C18 connected to U20/5,6 is a minor modification, which can be omitted at the discretion of the user, which slows down the signal transition to compensate for the additional delay imposed by the EX-OR gate in the other signal path. Because C18 is connected between the complementary outputs U20/5,6 it will have a different effect on different edges (due to the unequal high and low drive capabilities of the 74LS series TTL devices used in logic circuits). This is a benefit because the tiny ghost dot-fraction which is to be removed from one end of the displayed picture line does not simply want moving to the other end of the line, which would be the effect of a straight delay.
As always this is much ado about nothing, the imperfection which C18 is designed to remove is completely invisible to the average user. (If you want to search for it use the pixel block graphics at specific screen locations with the rest of the screen blank, and the brilliance control on your TV / Monitor advanced to twice its normal setting – you may just see a faint vertical line in the join between picture area and blank margin.)
The signal which now contains the pattern of dots, correctly blanked in the top and bottom margins, is now taken through another EX-OR gate U21/9,10,8. The output signal called "vid", from U21/8 is exactly the same as the input U21/10 provided U21/9 is low, i.e. P4 pins 1 and 2 are connected together. If they are not connected R20 pulls U21 pin 9 high and U21/10,8 behaves like an inverter, i.e. the signal "vid" from pin 8 is the inverse of the input signal on pin 10. This effect is known as "Invert All" because not only all the characters, but the margins as well are inverted, i.e. "normal" video this time is black characters on a white background, just as on a conventional printed page, and any "reversed" characters appear as white characters overlaid on a character size black "box". Some advice is offered in Section 2 of this Manual on the subject of not being too quick to dismiss this setting, as in some applications some people prefer it. The designers recommendation is to fit a SPST switch on the front panel (if fitted), so that all options are left entirely open.
There are two routes now for the "vid" signal; firstly (bottom left of diagram) to form a composite video output to drive a video monitor, and secondly (bottom right of diagram) to feed a high quality UHP Modulator which gives an output suitable for feeding a standard television receiver, via its aerial socket. As this latter circuit is the simpler to implement (all the complications being dealt with by the manufacturer of the UHF Modulator), this will be described first, after the following general remarks.
The two signals which are being brought together are "vid", which contains the pattern o f dots required, suitably blanked in the margins, and "S" which is the combined line sync. and frame sync. signal used to synchronise the display device. As all of the timing is fundamentally under the control of the master crystal controlled Z80A-CPU-based Timing generator, it is possible to ensure that no sync. changes are present in the video display period and vice versa.
This makes the circuit to combine the "vid" and "S" signals quite simple, and in fact just two resistors are all that is required to provide the composite signal which is needed to drive the UHF Modulator UM1. The precise levels chosen suit the requirements of the modulator, and are set by choosing appropriate values for R12 and R13.
Space for two extra resistors (R11 and R14) is provided, but these are not normally fitted. They could be selected for example to give different levels to suit some other modulator, past, present, or future. Since R11 and R14 are connected to the d.c. supply rails they permit variations in the signal which cannot be achieved simply by varying R12 and R13.
There will be some unit to unit variation in level because the signals depend on the voltage of an LS TTL logic "1", however the resistors have been chosen so that the modulator is driven by a signal which is larger than the minimum specified on the modulator data sheet so that it is sure to end up in the correct linear region of its characteristic in all circumstances.
The final part of the circuit to be described is shown at the bottom left of the diagram. The "vid" signal is buffered by U21/1,2,3 which is connected as a simple non-inverting buffer; similarly the "S" signal is buffered by U21/11,12,13 connected in the same way. In this case the buffers are not there in order to provide increased drive for the circuit which follows, instead they are there to ensure that the circuit which follows does not alter the levels of the circuit which precedes the buffers. This is important in the case of a card such as this which can drive both a TV receiver and a video monitor simultaneously; if alterations were made to say the video output components it would be far harder to get them right if they were driven from the same source as the modulator, because an alteration for one output might spoil the other.
Although U21 is not an open collector device, R15 and R19 have been provided to give a more accurate and defined logic "1", which takes some of the uncertainty out of the design of the rest of the circuit. The output U21/3 is reduced in amplitude by the potential divider formed by R16 and R17 so that it is a more suitable voltage for a video output to a monitor. The sync. output from U21/11 is shifted in level so that it swings below 0V, by the action of C15 and CR2. As C15 is a large (valued) capacitor it cannot charge or discharge quickly, and so its negative end (end 2) is forced to swing in amplitude to the same extent as its positive end (1). CR2 prevents end 2 of C15 from rising very much above 0V (this is called clamping) and so the sync. voltage applied as an input to end 2 of R18 is mostly a little over 0V, but falling a few volts minus when a sync. pulse is present. This causes a current to flow through R18 (and R16 and R17) and the resulting voltage dropped at ends 1 of the three resistors results in the sync. pulses being impressed onto what is now the composite video output. The three resistors can be juggled in value to alter the output if needed. This can be done by experiment, viewing the output on an oscilloscope, assuming it has a TVF trigger (for TV fields), or it makes a very interesting example of a calculation using Ohm's Law, Thevenin equivalent circuits and the like, for any academics who are members of our happy band.
The composite video output is deliberately not a.c. coupled since very high quality video monitors may keep the video path d.c. coupled throughout. (For the penalty which can result from not doing this see the part of Section 4 of this Manual which discusses a.c. coupling in video circuits.)
This hardly needs any explanation, so this part of the description can mercifully be fairly brief.
A Key to the various symbols used are described at the foot of the drawing.
All of the decoupling capacitors are shown on this drawing, although for electrical reasons they are distributed widely about the board.
This concludes the detailed circuit description.