3. General Circuit Description

3.1
The circuit diagram (No. 101810) covers 6 sheets, pages 33-38 , and these represent convenient subdivisions for description.

3.2
Sheet 1 (Page 33), shows the crystal controlled clock oscillator. It has two outputs: ZŲ, which drives the CPU chip (IC10, Z80), and 'RCLK', which drives the bus via edge connector pin A33.

3.3
Sheet 2 (Page 34), is the diagram of the reset circuit. The output 'NRST' is used on the card and is also taken to the edge connector pin A21.

3.4
Sheet 3 (Page 35), shows the CPU chip itself, the power on jump circuit and 4K page decoder. (There is space on the board for an EPROM which can be located at any 4K boundary).

3.5
Sheet 4 (Page 36), shows the EPROM (IC 11). IC 2 is a dual flip-flop. The IC2a output ’PJUMP' is used for the 'POWER-ON-JUMP’ feature, and the IC26 output is used to select the EPROM. Under software control IC2a can be reset, to remove the effect of the 'POWER-ON-JUMP’ and IC2b can be reset to disable IC11, (so that some other memory devices, e.g. system dynamic RAM, can use the same addresses).

3.6
Arrangements like this are invaluable in 'floppy disc' systems: (all the programs in such a system are generally kept on the discs, the only firmware necessary being a 'bootstrap' PROM in this case IC11, which is in circuit only long enough to get the system running, and which is then switched out).

3.7
Sheet 5 (Page 37) is the diagram of the buffers to the edge connector. The 8 bit data bus is bidirectional (IC17), and all other signals (address and control) are unidirectional (IC7, IC8, IC13).